libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
emu_common.h
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1/** @addtogroup emu_defines
2 */
3/*
4 * This file is part of the libopencm3 project.
5 *
6 * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
7 *
8 * This library is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public License
19 * along with this library. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#pragma once
23
24#include <libopencm3/efm32/memorymap.h>
25#include <libopencm3/cm3/common.h>
26
27/**@{*/
28
29#define EMU_CTRL MMIO32(EMU_BASE + 0x000)
30#define EMU_LOCK MMIO32(EMU_BASE + 0x008)
31#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024)
32#define EMU_EM4CONF MMIO32(EMU_BASE + 0x02C)
33#define EMU_BUCTRL MMIO32(EMU_BASE + 0x030)
34#define EMU_PWRCONF MMIO32(EMU_BASE + 0x034)
35#define EMU_BUINACT MMIO32(EMU_BASE + 0x038)
36#define EMU_BUACT MMIO32(EMU_BASE + 0x03C)
37#define EMU_STATUS MMIO32(EMU_BASE + 0x040)
38#define EMU_ROUTE MMIO32(EMU_BASE + 0x044)
39#define EMU_IF MMIO32(EMU_BASE + 0x048)
40#define EMU_IFS MMIO32(EMU_BASE + 0x04C)
41#define EMU_IFC MMIO32(EMU_BASE + 0x050)
42#define EMU_IEN MMIO32(EMU_BASE + 0x054)
43#define EMU_BUBODBUVINCAL MMIO32(EMU_BASE + 0x058)
44#define EMU_BUBODUNREGCAL MMIO32(EMU_BASE + 0x05C)
45
46/* EMU_CTRL */
47#define EMU_CTRL_EM4CTRL_SHIFT (2)
48#define EMU_CTRL_EM4CTRL_MASK (0x3 << EMU_CTRL_EM4CTRL_SHIFT)
49#define EMU_CTLR_EM4CTRL(v) \
50 (((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK)
51
52#define EMU_CTRL_EM2BLOCK (1 << 1)
53#define EMU_CTRL_EMVREG (1 << 0)
54
55/* EMU_LOCK */
56#define EMU_LOCK_LOCKKEY_MASK (0xFFFF)
57#define EMU_LOCK_LOCKKEY_LOCK (0)
58#define EMU_LOCK_LOCKKEY_UNLOCK (0xADE8)
59
60/* EMU_AUXCTRL */
61#define EMU_AUXCTRL_HRCCLR (1 << 0)
62
63/* EMU_EM4CONF */
64#define EMU_EM4CONF_LOCKCONF (1 << 16)
65#define EMU_EM4CONF_BUBODRSTDIS (1 << 4)
66
67#define EMU_EM4CONF_OSC_SHIFT (2)
68#define EMU_EM4CONF_OSC_MASK (0x3 << EMU_EM4CONF_OSC_SHIFT)
69#define EMU_EM4CONF_OSC(v) \
70 (((v) << EMU_EM4CONF_OSC_SHIFT) & EMU_EM4CONF_OSC_MASK)
71#define EMU_EM4CONF_OSC_ULFRCO 0
72#define EMU_EM4CONF_OSC_LFRCO 1
73#define EMU_EM4CONF_OSC_LFXO 2
74
75#define EMU_EM4CONF_BURTCWU (1 << 1)
76#define EMU_EM4CONF_VREGEN (1 << 0)
77
78/* EMU_BUCTRL */
79#define EMU_BUCTRL_PROBE_SHIFT (5)
80#define EMU_BUCTRL_PROBE_MASK (0x3 << EMU_BUCTRL_PROBE_SHIFT)
81#define EMU_BUCTRL_PROBE(v) \
82 (((v) << EMU_BUCTRL_PROBE_SHIFT) & EMU_BUCTRL_PROBE_MASK)
83#define EMU_BUCTRL_PROBE_DISABLE 0
84#define EMU_BUCTRL_PROBE_VDDDREG 1
85#define EMU_BUCTRL_PROBE_BUIN 2
86#define EMU_BUCTRL_PROBE_BUOUT 3
87
88#define EMU_BUCTRL_BUMODEBODEN (1 << 3)
89#define EMU_BUCTRL_BODCAL (1 << 2)
90#define EMU_BUCTRL_STATEN (1 << 1)
91#define EMU_BUCTRL_EN (1 << 0)
92
93/* EMU_PWRCONF */
94#define EMU_PWRCONF_PWRRES_SHIFT (3)
95#define EMU_PWRCONF_PWRRES_MASK (0x3 << EMU_PWRCONF_PWRRES_SHIFT)
96#define EMU_PWRCONF_PWRRES(v) \
97 (((v) << EMU_PWRCONF_PWRRES_SHIFT) & EMU_PWRCONF_PWRRES_MASK)
98#define EMU_PWRCONF_PWRRES_DISABLE 0
99#define EMU_PWRCONF_PWRRES_VDDDREG 1
100#define EMU_PWRCONF_PWRRES_BUIN 2
101#define EMU_PWRCONF_PWRRES_BUOUT 3
102
103#define EMU_PWRCONF_VOUTSTRONG (1 << 2)
104#define EMU_PWRCONF_VOUTMED (1 << 1)
105#define EMU_PWRCONF_VOUTWEAK (1 << 0)
106
107/* EMU_BUINACT */
108#define EMU_BUINACT_PWRCON_SHIFT (5)
109#define EMU_BUINACT_PWRCON_MASK (0x3 << EMU_BUINACT_PWRCON_SHIFT)
110#define EMU_BUINACT_PWRCON(v) \
111 (((v) << EMU_BUINACT_PWRCON_SHIFT) & EMU_BUINACT_PWRCON_MASK)
112#define EMU_BUINACT_PWRCON_NONE 0
113#define EMU_BUINACT_PWRCON_BUMAIN 1
114#define EMU_BUINACT_PWRCON_MAINBU 2
115#define EMU_BUINACT_PWRCON_NODIODE 3
116
117#define EMU_BUINACT_BUENRANGE_SHIFT (3)
118#define EMU_BUINACT_BUENRANGE_MASK (0x3 << EMU_BUINACT_BUENRANGE_SHIFT)
119#define EMU_BUINACT_BUENRANGE(v) \
120 (((v) << EMU_BUINACT_BUENRANGE_SHIFT) & EMU_BUINACT_BUENRANGE_MASK)
121
122#define EMU_BUINACT_BUENTHRES_SHIFT (0)
123#define EMU_BUINACT_BUENTHRES_MASK (0x7 << EMU_BUINACT_BUENTHRES_SHIFT)
124#define EMU_BUINACT_BUENTHRES(v) \
125 (((v) << EMU_BUINACT_BUENTHRES_SHIFT) & EMU_BUINACT_BUENTHRES_MASK)
126
127/* EMU_BUACT */
128#define EMU_BUACT_PWRCON_SHIFT (5)
129#define EMU_BUACT_PWRCON_MASK (0x3 << EMU_BUACT_PWRCON_SHIFT)
130#define EMU_BUACT_PWRCON(v) \
131 (((v) << EMU_BUACT_PWRCON_SHIFT) & EMU_BUACT_PWRCON_MASK)
132#define EMU_BUACT_PWRCON_NONE 0
133#define EMU_BUACT_PWRCON_BUMAIN 1
134#define EMU_BUACT_PWRCON_MAINBU 2
135#define EMU_BUACT_PWRCON_NODIODE 3
136
137#define EMU_BUACT_BUEXRANGE_SHIFT (3)
138#define EMU_BUACT_BUEXRANGE_MASK (0x3 << EMU_BUACT_BUEXRANGE_SHIFT)
139#define EMU_BUACT_BUEXRANGE(v) \
140 (((v) << EMU_BUACT_BUEXRANGE_SHIFT) & EMU_BUACT_BUEXRANGE_MASK)
141
142#define EMU_BUACT_BUEXTHRES_SHIFT (0)
143#define EMU_BUACT_BUEXTHRES_MASK (0x7 << EMU_BUACT_BUEXTHRES_SHIFT)
144#define EMU_BUACT_BUEXTHRES(v) \
145 (((v) << EMU_BUACT_BUEXTHRES_SHIFT) & EMU_BUACT_BUEXTHRES_MASK)
146
147/* EMU_STATUS */
148#define EMU_STATUS_BURDY (1 << 0)
149
150/* EMU_ROUTE */
151#define EMU_ROUTE_BUVINPEN (1 << 0)
152
153/* EMU_IF */
154#define EMU_IF_BURDY (1 << 0)
155
156/* EMU_IFS */
157#define EMU_IFS_BURDY (1 << 0)
158
159/* EMU_IFC */
160#define EMU_IFC_BURDY (1 << 0)
161
162/* EMU_IEN */
163#define EMU_IEN_BURDY (1 << 0)
164
165/* EMU_BUBODBUVINCAL */
166#define EMU_BUBODBUVINCAL_RANGE_SHIFT (3)
167#define EMU_BUBODBUVINCAL_RANGE_MASK (0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT)
168#define EMU_BUBODBUVINCAL_RANGE(v) \
169 (((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & \
170 EMU_BUBODBUVINCAL_RANGE_MASK)
171
172#define EMU_BUBODBUVINCAL_THRES_SHIFT (0)
173#define EMU_BUBODBUVINCAL_THRES_MASK (0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT)
174#define EMU_BUBODBUVINCAL_THRES(v) \
175 (((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & \
176 EMU_BUBODBUVINCAL_THRES_MASK)
177
178/* EMU_BUBODUNREGCAL */
179#define EMU_BUBODUNREGCAL_RANGE_SHIFT (3)
180#define EMU_BUBODUNREGCAL_RANGE_MASK (0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT)
181#define EMU_BUBODUNREGCAL_RANGE(v) \
182 (((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & \
183 EMU_BUBODUNREGCAL_RANGE_MASK)
184
185#define EMU_BUBODUNREGCAL_THRES_SHIFT (0)
186#define EMU_BUBODUNREGCAL_THRES_MASK (0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT)
187#define EMU_BUBODUNREGCAL_THRES(v) \
188 (((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \
189 EMU_BUBODUNREGCAL_THRES_MASK)
190
191/**@}*/
memorymap.h
Dispatcher for the base address definitions, depending on the particular Gecko family.