libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
msc_common.h
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1/** @addtogroup msc_defines
2 */
3/*
4 * This file is part of the libopencm3 project.
5 *
6 * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
7 *
8 * This library is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public License
19 * along with this library. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#pragma once
23
24#include <libopencm3/efm32/memorymap.h>
25#include <libopencm3/cm3/common.h>
26
27/**@{*/
28
29#define MSC_CTRL MMIO32(MSC_BASE + 0x000)
30#define MSC_READCTRL MMIO32(MSC_BASE + 0x004)
31#define MSC_WRITECTRL MMIO32(MSC_BASE + 0x008)
32#define MSC_WRITECMD MMIO32(MSC_BASE + 0x00C)
33#define MSC_ADDRB MMIO32(MSC_BASE + 0x010)
34#define MSC_WDATA MMIO32(MSC_BASE + 0x018)
35#define MSC_STATUS MMIO32(MSC_BASE + 0x01C)
36#define MSC_IF MMIO32(MSC_BASE + 0x02C)
37#define MSC_IFS MMIO32(MSC_BASE + 0x030)
38#define MSC_IFC MMIO32(MSC_BASE + 0x034)
39#define MSC_IEN MMIO32(MSC_BASE + 0x038)
40#define MSC_LOCK MMIO32(MSC_BASE + 0x03C)
41#define MSC_CMD MMIO32(MSC_BASE + 0x040)
42#define MSC_CACHEHITS MMIO32(MSC_BASE + 0x044)
43#define MSC_CACHEMISSES MMIO32(MSC_BASE + 0x048)
44#define MSC_TIMEBASE MMIO32(MSC_BASE + 0x050)
45#define MSC_MASSLOCK MMIO32(MSC_BASE + 0x054)
46
47/* MSC_CTRL */
48#define MSC_CTRL_BUSFAULT (1 << 0)
49
50/* MSC_READCTRL */
51#define MSC_READCTRL_BUSSTRATEGY_SHIFT (16)
52#define MSC_READCTRL_BUSSTRATEGY_MASK \
53 (0x3 << MSC_READCTRL_BUSSTRATEGY_SHIFT)
54#define MSC_READCTRL_BUSSTRATEGY(v) \
55 (((v) << MSC_READCTRL_BUSSTRATEGY_SHIFT) & \
56 MSC_READCTRL_BUSSTRATEGY_MASK)
57
58#define MSC_READCTRL_BUSSTRATEGY_CPU MSC_READCTRL_BUSSTRATEGY(0)
59#define MSC_READCTRL_BUSSTRATEGY_DMA MSC_READCTRL_BUSSTRATEGY(1)
60#define MSC_READCTRL_BUSSTRATEGY_DMAEM1 MSC_READCTRL_BUSSTRATEGY(2)
61#define MSC_READCTRL_BUSSTRATEGY_NONE MSC_READCTRL_BUSSTRATEGY(3)
62
63#define MSC_READCTRL_RAMCEN (1 << 7)
64#define MSC_READCTRL_EBICDIS (1 << 6)
65#define MSC_READCTRL_ICCDIS (1 << 5)
66#define MSC_READCTRL_AIDIS (1 << 4)
67#define MSC_READCTRL_IFCDIS (1 << 3)
68
69#define MSC_READCTRL_MODE_SHIFT (0)
70#define MSC_READCTRL_MODE_MASK (0x7 << MSC_READCTRL_MODE_SHIFT)
71#define MSC_READCTRL_MODE(v) \
72 (((v) << MSC_READCTRL_MODE_SHIFT) & MSC_READCTRL_MODE_MASK)
73#define MSC_READCTRL_MODE_WS0 0
74#define MSC_READCTRL_MODE_WS1 1
75#define MSC_READCTRL_MODE_WS0SCBTP 2
76#define MSC_READCTRL_MODE_WS1SCBTP 3
77#define MSC_READCTRL_MODE_WS2 4
78#define MSC_READCTRL_MODE_WS2SCBTP 5
79
80/* MSC_WRITECTRL */
81#define MSC_WRITECTRL_IRQERASEABORT (1 << 1)
82#define MSC_WRITECTRL_WREN (1 << 0)
83
84/* MSC_WRITECMD */
85#define MSC_WRITECMD_CLEARWDATA (1 << 12)
86#define MSC_WRITECMD_ERASEMAIN0 (1 << 8)
87#define MSC_WRITECMD_ERASEABORT (1 << 5)
88#define MSC_WRITECMD_WRITETRIG (1 << 4)
89#define MSC_WRITECMD_WRITEONCE (1 << 3)
90#define MSC_WRITECMD_WRITEEND (1 << 2)
91#define MSC_WRITECMD_ERASEPAGE (1 << 1)
92#define MSC_WRITECMD_LADDRIM (1 << 0)
93
94/* MSC_STATUS */
95#define MSC_STATUS_PCRUNNING (1 << 6)
96#define MSC_STATUS_ERASEABORTED (1 << 5)
97#define MSC_STATUS_WORDTIMEOUT (1 << 4)
98#define MSC_STATUS_WDATAREADY (1 << 3)
99#define MSC_STATUS_INVADDR (1 << 2)
100#define MSC_STATUS_LOCKED (1 << 1)
101#define MSC_STATUS_BUSY (1 << 0)
102
103/* MSC_IF */
104#define MSC_IF_CMOF (1 << 3)
105#define MSC_IF_CHOF (1 << 2)
106#define MSC_IF_WRITE (1 << 1)
107#define MSC_IF_ERASE (1 << 0)
108
109/* MSC_IFS */
110#define MSC_IFS_CMOF (1 << 3)
111#define MSC_IFS_CHOF (1 << 2)
112#define MSC_IFS_WRITE (1 << 1)
113#define MSC_IFS_ERASE (1 << 0)
114
115/* MSC_IFC */
116#define MSC_IFC_CMOF (1 << 3)
117#define MSC_IFC_CHOF (1 << 2)
118#define MSC_IFC_WRITE (1 << 1)
119#define MSC_IFC_ERASE (1 << 0)
120
121/* MSC_*IEN */
122#define MSC_IEN_CMOF (1 << 3)
123#define MSC_IEN_CHOF (1 << 2)
124#define MSC_IEN_WRITE (1 << 1)
125#define MSC_IEN_ERASE (1 << 0)
126
127/* MSC_LOCK */
128#define MSC_LOCK_LOCKKEY_SHIFT (0)
129#define MSC_LOCK_LOCKKEY(v) ((v) << MSC_LOCK_LOCKKEY_SHIFT)
130#define MSC_LOCK_LOCKKEY_UNLOCKED MSC_LOCK_LOCKKEY(0)
131#define MSC_LOCK_LOCKKEY_LOCKED MSC_LOCK_LOCKKEY(1)
132#define MSC_LOCK_LOCKKEY_LOCK MSC_LOCK_LOCKKEY(0)
133#define MSC_LOCK_LOCKKEY_UNLOCK MSC_LOCK_LOCKKEY(0x1B71)
134
135/* MSC_CMD */
136#define MSC_CMD_STOPPC (1 << 2)
137#define MSC_CMD_STARTPC (1 << 1)
138#define MSC_CMD_INVCACHE (1 << 0)
139
140/* MSC_TIMEBASE */
141#define MSC_TIMEBASE_PERIOD (1 << 16)
142
143#define MSC_TIMEBASE_BASE_SHIFT (0)
144#define MSC_TIMEBASE_BASE_MASK (0x3F << MSC_TIMEBASE_BASE_SHIFT)
145#define MSC_TIMEBASE_BASE(v) \
146 (((v) << MSC_TIMEBASE_BASE_SHIFT) & MSC_TIMEBASE_BASE_MASK)
147
148/* MSC_MASSLOCK */
149#define MSC_MASSLOCK_LOCKKEY_SHIFT (0)
150#define MSC_MASSLOCK_LOCKKEY(v) ((v) << MSC_MASSLOCK_LOCKKEY_SHIFT)
151#define MSC_MASSLOCK_LOCKKEY_UNLOCKED MSC_MASSLOCK_LOCKKEY(0)
152#define MSC_MASSLOCK_LOCKKEY_LOCKED MSC_MASSLOCK_LOCKKEY(1)
153#define MSC_MASSLOCK_LOCKKEY_LOCK MSC_MASSLOCK_LOCKKEY(0)
154#define MSC_MASSLOCK_LOCKKEY_UNLOCK MSC_MASSLOCK_LOCKKEY(0x631A)
155
156/**@}*/
memorymap.h
Dispatcher for the base address definitions, depending on the particular Gecko family.