libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
itm.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_CM3_ITM_H
21#define LIBOPENCM3_CM3_ITM_H
22
23/**
24 * @defgroup cm_itm Cortex-M Instrumentation Trace Macrocell (ITM)
25 * @ingroup CM3_defines
26 * @{
27 */
28
29/* Those defined only on ARMv7 and above */
30#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
31#error "Instrumentation Trace Macrocell not available in CM0"
32#endif
33
34/* --- ITM registers ------------------------------------------------------- */
35
36/* Stimulus Port x (ITM_STIM<sz>(x)) */
37#define ITM_STIM8(n) (MMIO8(ITM_BASE + ((n)*4)))
38#define ITM_STIM16(n) (MMIO16(ITM_BASE + ((n)*4)))
39#define ITM_STIM32(n) (MMIO32(ITM_BASE + ((n)*4)))
40
41/* Trace Enable ports (ITM_TER[x]) */
42#define ITM_TER (&MMIO32(ITM_BASE + 0xE00))
43
44/* Trace Privilege (ITM_TPR) */
45#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
46
47/* Trace Control (ITM_TCR) */
48#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
49
50/* CoreSight Lock Status Register for this peripheral */
51#define ITM_LSR MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
52/* CoreSight Lock Access Register for this peripheral */
53#define ITM_LAR MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
54
55/* TODO: PID, CID */
56
57/* --- ITM_STIM values ----------------------------------------------------- */
58
59/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
60/* Bits 31:1 - RAZ */
61#define ITM_STIM_FIFOREADY (1 << 0)
62
63/* --- ITM_TER values ------------------------------------------------------ */
64
65/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
66
67/* --- ITM_TPR values ------------------------------------------------------ */
68/*
69 * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
70 * 0: User access allowed to stimulus ports
71 * 1: Privileged access only to stimulus ports
72 */
73
74/* --- ITM_TCR values ------------------------------------------------------ */
75
76/* Bits 31:24 - Reserved */
77#define ITM_TCR_BUSY (1 << 23)
78#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
79/* Bits 15:10 - Reserved */
80#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
81#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
82#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
83#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
84#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
85/* Bits 7:5 - Reserved */
86#define ITM_TCR_SWOENA (1 << 4)
87#define ITM_TCR_TXENA (1 << 3)
88#define ITM_TCR_SYNCENA (1 << 2)
89#define ITM_TCR_TSENA (1 << 1)
90#define ITM_TCR_ITMENA (1 << 0)
91
92/**@}*/
93
94#endif