libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
ssi.h
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1/** @defgroup ssi_defines Synchronous Serial Interface
2 *
3 * @brief <b>Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI)</b>
4 *
5 * @ingroup LM4Fxx_defines
6 *
7 * @version 1.0.0
8 *
9 * @author @htmlonly &copy; @endhtmlonly 2014
10 * Tiago Costa <nippius+github@gmail.com>
11 *
12 * @date 11 June 2014
13 *
14 * LGPL License Terms @ref lgpl_license
15 */
16
17/*
18 * This file is part of the libopencm3 project.
19 *
20 * Copyright (C) 2014 Tiago Costa <nippius+github@gmail.com>
21 *
22 * This library is free software: you can redistribute it and/or modify
23 * it under the terms of the GNU Lesser General Public License as published by
24 * the Free Software Foundation, either version 3 of the License, or
25 * (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public License
33 * along with this library. If not, see <http://www.gnu.org/licenses/>.
34 */
35
36#ifndef LM4F_SSI_H
37#define LM4F_SSI_H
38
39/**@{*/
40
41#include <libopencm3/cm3/common.h>
42#include <libopencm3/lm4f/memorymap.h>
43
44/* =============================================================================
45 * Convenience macros
46 * ---------------------------------------------------------------------------*/
47/** @defgroup ssi_base SSI register base addresses
48 * @{*/
49#define SSI0 SSI0_BASE
50#define SSI1 SSI1_BASE
51#define SSI2 SSI2_BASE
52#define SSI3 SSI3_BASE
53/** @} */
54
55/* =============================================================================
56 * SSI registers
57 * ---------------------------------------------------------------------------*/
58
59/* SSI Control 0 */
60#define SSI_CR0(port) MMIO32((port) + 0x000)
61
62/* SSI Control 1 */
63#define SSI_CR1(port) MMIO32((port) + 0x004)
64
65/* SSI Data */
66#define SSI_DR(port) MMIO32((port) + 0x008)
67
68/* SSI Satus */
69#define SSI_SR(port) MMIO32((port) + 0x00C)
70
71/* SSI Clock Prescale */
72#define SSI_CPSR(port) MMIO32((port) + 0x010)
73
74/* SSI Interrupt Mask */
75#define SSI_IM(port) MMIO32((port) + 0x014)
76
77/* SSI Raw Interrupt Status */
78#define SSI_RIS(port) MMIO32((port) + 0x018)
79
80/* SSI Masked Interrupt Status */
81#define SSI_MIS(port) MMIO32((port) + 0x01C)
82
83/* SSI Interrupt Clear */
84#define SSI_ICR(port) MMIO32((port) + 0x020)
85
86/* SSI DMA Control */
87#define SSI_DMACTL(port) MMIO32((port) + 0x024)
88
89/* SSI Clock Configuration */
90#define SSI_CC(port) MMIO32((port) + 0xFC8)
91
92/* SSI Peripheral Identification */
93#define SSI_PERIPH_ID4(port) MMIO32((port) + 0xFD0)
94#define SSI_PERIPH_ID5(port) MMIO32((port) + 0xFD4)
95#define SSI_PERIPH_ID6(port) MMIO32((port) + 0xFD8)
96#define SSI_PERIPH_ID7(port) MMIO32((port) + 0xFDC)
97#define SSI_PERIPH_ID0(port) MMIO32((port) + 0xFE0)
98#define SSI_PERIPH_ID1(port) MMIO32((port) + 0xFE4)
99#define SSI_PERIPH_ID2(port) MMIO32((port) + 0xFE8)
100#define SSI_PERIPH_ID3(port) MMIO32((port) + 0xFEC)
101
102/* SSI PrimeCell Identification */
103#define SSI_PCELL_ID0(port) MMIO32((port) + 0xFF0)
104#define SSI_PCELL_ID1(port) MMIO32((port) + 0xFF4)
105#define SSI_PCELL_ID2(port) MMIO32((port) + 0xFF8)
106#define SSI_PCELL_ID3(port) MMIO32((port) + 0xFFC)
107
108/* =============================================================================
109 * Function prototypes
110 * ---------------------------------------------------------------------------*/
111BEGIN_DECLS
112
113END_DECLS
114
115/**@}*/
116
117#endif /* LM4F_SSI_H */
118
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33