libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
lpc13xx/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LPC13XX_MEMORYMAP_H
21#define LPC13XX_MEMORYMAP_H
22
23#include <libopencm3/cm3/common.h>
24
25/* --- LPC13XX specific peripheral definitions ----------------------------- */
26
27/* Memory map for all busses */
28#define PERIPH_BASE_APB (0x40000000U)
29#define PERIPH_BASE_AHB (0x50000000U)
30
31/* Register boundary addresses */
32
33/* APB */
34#define I2C_BASE (PERIPH_BASE_APB + 0x00000)
35#define WDT_BASE (PERIPH_BASE_APB + 0x04000)
36#define UART_BASE (PERIPH_BASE_APB + 0x08000)
37#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000)
38#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000)
39#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000)
40#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000)
41#define ADC_BASE (PERIPH_BASE_APB + 0x1c000)
42#define USB_BASE (PERIPH_BASE_APB + 0x20000)
43/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */
44#define PMU_BASE (PERIPH_BASE_APB + 0x38000)
45#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000)
46#define SSP_BASE (PERIPH_BASE_APB + 0x40000)
47#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000)
48#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000)
49/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */
50
51/* AHB */
52#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000)
53#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000)
54#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000)
55#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000)
56/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */
57
58#endif