libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
51/ficr.h
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1/** @defgroup ficr_defines FICR Defines
2 *
3 * @brief <b>Defined Constants and Types for the NRF51xx Factory information
4 * configuration registers</b>
5 *
6 * @ingroup NRF51xx_defines
7 *
8 * @version 1.0.0
9 *
10 * @date Nov 2021
11 *
12 *LGPL License Terms @ref lgpl_license
13 */
14/*
15 * This file is part of the libopencm3 project.
16 *
17 * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
18 * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34#pragma once
35
36#include <libopencm3/cm3/common.h>
37#include <libopencm3/nrf/memorymap.h>
38#include <libopencm3/nrf/common/ficr.h>
39
40/* Deprecated by Nordic */
41#define FICR_CLENR0 MMIO32(FICR_BASE + 0x028)
42/* Deprecated by Nordic */
43#define FICR_PPFC MMIO32(FICR_BASE + 0x02C)
44
45#define FICR_NUMRAMBLOCK MMIO32(FICR_BASE + 0x034)
46#define FICR_SIZERAMBLOCKS MMIO32(FICR_BASE + 0x038)
47
48/* Deprecated by Nordic */
49#define FICR_SIZERAMBLOCK(n) MMIO32(FICR_BASE + 0x038 + 0x4 * (n))
50
51#define FICR_CONFIGID MMIO32(FICR_BASE + 0x05C)
52
53#define FICR_OVERRIDEEN MMIO32(FICR_BASE + 0x0AC)
54
55/* Override values for Nordic Semi proprietary NRF 1Mbit mode */
56#define FICR_NRF_1MBIT(n) MMIO32(FICR_BASE + 0x0B0 + 0x4 * (n))
57#define FICR_NRF_1MBIT0 FICR_NRF_1MBIT(0)
58#define FICR_NRF_1MBIT1 FICR_NRF_1MBIT(1)
59#define FICR_NRF_1MBIT2 FICR_NRF_1MBIT(2)
60#define FICR_NRF_1MBIT3 FICR_NRF_1MBIT(3)
61#define FICR_NRF_1MBIT4 FICR_NRF_1MBIT(4)
62
63/* Override values for BLE 1Mbit mode */
64#define FICR_BLE_1MBIT(n) MMIO32(FICR_BASE + 0x0EC + 0x4 * (n))
65#define FICR_BLE_1MBIT0 FICR_BLE_1MBIT(0)
66#define FICR_BLE_1MBIT1 FICR_BLE_1MBIT(1)
67#define FICR_BLE_1MBIT2 FICR_BLE_1MBIT(2)
68#define FICR_BLE_1MBIT3 FICR_BLE_1MBIT(3)
69#define FICR_BLE_1MBIT4 FICR_BLE_1MBIT(4)
70
71#define FICR_OVERRIDEEN_NRF_1MBIT (1 << 0)
72#define FICR_OVERRIDEEN_BLE_1MBIT (1 << 3)
73