libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
common/ppi.h
Go to the documentation of this file.
1/** @addtogroup ppi_defines
2 *
3 * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
4 * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
5 *
6 **/
7
8/*
9 * This file is part of the libopencm3 project.
10 *
11 * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
12 * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
13 *
14 * This library is free software: you can redistribute it and/or modify
15 * it under the terms of the GNU Lesser General Public License as published by
16 * the Free Software Foundation, either version 3 of the License, or
17 * (at your option) any later version.
18 *
19 * This library is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU Lesser General Public License for more details.
23 *
24 * You should have received a copy of the GNU Lesser General Public License
25 * along with this library. If not, see <http://www.gnu.org/licenses/>.
26 */
27
28#pragma once
29
32/**@{*/
33
34/* Programmable Peripheral Interconnect */
35
36/* Tasks */
37
38#define PPI_TASK_CHG_EN(n) MMIO32(PPI_BASE + 0x8 * (n))
39#define PPI_TASK_CHG_DIS(n) MMIO32(PPI_BASE + 0x8 * (n) + 0x4)
40
41/* Registers */
42
43#define PPI_CHEN MMIO32(PPI_BASE + 0x500)
44#define PPI_CHENSET MMIO32(PPI_BASE + 0x504)
45#define PPI_CHENCLR MMIO32(PPI_BASE + 0x508)
46
47/* Event End Point n = 0 .. 15 */
48#define PPI_CH_EEP(n) MMIO32(PPI_BASE + 0x510 + 0x8 * (n))
49/* Task End Point n = 0 .. 15 */
50#define PPI_CH_TEP(n) MMIO32(PPI_BASE + 0x514 + 0x8 * (n))
51
52/* Channel Groups */
53#define PPI_CHG(n) MMIO32(PPI_BASE + 0x800 + 0x4 * (n))
54
55#define PPI_CH(n) (1 << (n))
56/** @addtogroup PPI Channel identifiers
57 * @{
58 */
59#define PPI_CH0 (1 << 0)
60#define PPI_CH1 (1 << 1)
61#define PPI_CH2 (1 << 2)
62#define PPI_CH3 (1 << 3)
63#define PPI_CH4 (1 << 4)
64#define PPI_CH5 (1 << 5)
65#define PPI_CH6 (1 << 6)
66#define PPI_CH7 (1 << 7)
67#define PPI_CH8 (1 << 8)
68#define PPI_CH9 (1 << 9)
69#define PPI_CH10 (1 << 10)
70#define PPI_CH11 (1 << 11)
71#define PPI_CH12 (1 << 12)
72#define PPI_CH13 (1 << 13)
73#define PPI_CH14 (1 << 14)
74#define PPI_CH15 (1 << 15)
75/* Channels 16-19 are reserved */
76#define PPI_CH20 (1 << 20)
77#define PPI_CH21 (1 << 21)
78#define PPI_CH22 (1 << 22)
79#define PPI_CH23 (1 << 23)
80#define PPI_CH24 (1 << 24)
81#define PPI_CH25 (1 << 25)
82#define PPI_CH26 (1 << 26)
83#define PPI_CH27 (1 << 27)
84#define PPI_CH28 (1 << 28)
85#define PPI_CH29 (1 << 29)
86#define PPI_CH30 (1 << 30)
87#define PPI_CH31 (1 << 31)
88
89/**@}*/
90
91#define PPI_MAX_PROG_CHANNEL (15)
92
93/* Preprogrammed channels */
94/* TIMER0->EVENTS_COMPARE0 -- RADIO->TASKS_TXEN */
95#define PPI_CH_TMR0CC0_RADIOTXEN PPI_CH20
96
97/* TIMER0->EVENTS_COMPARE0 -- RADIO->TASKS_RXEN */
98#define PPI_CH_TMR0CC0_RADIORXEN PPI_CH21
99
100/* TIMER0->EVENTS_COMPARE1 -- RADIO->TASKS_DISABLE */
101#define PPI_CH_TMR0CC1_RADIODIS PPI_CH22
102
103/* RADIO->EVENTS_BCMATCH -- AAR->TASKS_START */
104#define PPI_CH_RADIOBCMATCH_AARSTART PPI_CH23
105
106/* RADIO->EVENTS_READY -- CCM->TASKS_KSGEN */
107#define PPI_CH_RADIOREADY_CCMKSGEN PPI_CH24
108
109/* RADIO->EVENTS_ADDRESS -- CCM->TASKS_CRYPT */
110#define PPI_CH_RADIOADDR_CCMCRYPT PPI_CH25
111
112/* RADIO->EVENTS_ADDRESS -- TIMER0->TASKS_CAPTURE1 */
113#define PPI_CH_RADIOADDR_TMR0CAPT1 PPI_CH26
114
115/* RADIO->EVENTS_END -- TIMER0->TASKS_CAPTURE2 */
116#define PPI_CH_RADIOEND_TMR0CAPT2 PPI_CH27
117
118/* RTC0->EVENTS_COMPARE[0] -- RADIO->TASKS_TXEN */
119#define PPI_CH_RTC0CC0_RADIOTXEN PPI_CH28
120
121/* RTC0->EVENTS_COMPARE[0] -- RADIO->TASKS_RXEN */
122#define PPI_CH_RTC0CC0_RADIORXEN PPI_CH29
123
124/* RTC0->EVENTS_COMPARE[0] -- TIMER0->TASKS_CLEAR */
125#define PPI_CH_RTC0CC0_TMR0CLEAR PPI_CH30
126
127/* RTC0->EVENTS_COMPARE[0] -- TIMER0->TASKS_START */
128#define PPI_CH_RTC0CC0_TMR0START PPI_CH31
129/**@}*/
130
132
133void ppi_configure_channel(uint8_t chan_num, uint32_t eep, uint32_t tep);
134void ppi_enable_channels(uint32_t channels);
135void ppi_disable_channels(uint32_t channels);
136
137void ppi_set_group(uint8_t group, uint32_t channels);
138void ppi_enable_group(uint8_t group);
139void ppi_disable_group(uint8_t group);
140
141/* Simpler API, that requires the client to store channel map. */
142uint8_t ppi_add_channel(uint32_t *chan_map, uint32_t eep, uint32_t tep, bool enable);
143void ppi_remove_channel(uint32_t *chan_map, uint8_t chan_num);
144
146
147
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void ppi_configure_channel(uint8_t chan_num, uint32_t eep, uint32_t tep)
Configure PPI Channel.
Definition: ppi.c:43
void ppi_enable_group(uint8_t group)
Enable previously configured group of channels.
Definition: ppi.c:81
void ppi_enable_channels(uint32_t channels)
Enable PPI channels, given the channels mask.
Definition: ppi.c:53
void ppi_remove_channel(uint32_t *chan_map, uint8_t chan_num)
Disable channel and remove it from the map of used channels.
Definition: ppi.c:139
void ppi_disable_channels(uint32_t channels)
Disable PPI channels, given the channels mask.
Definition: ppi.c:62
void ppi_set_group(uint8_t group, uint32_t channels)
Set channels group, given channels mask.
Definition: ppi.c:72
void ppi_disable_group(uint8_t group)
Disable previously configured group of channels.
Definition: ppi.c:90
uint8_t ppi_add_channel(uint32_t *chan_map, uint32_t eep, uint32_t tep, bool enable)
Configure new channel.
Definition: ppi.c:106