libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
pmc_common_3a3u3x.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
5 * Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#if defined(LIBOPENCM3_PMC_H)
22
23#ifndef LIBOPENCM3_PMC_COMMON_3A3U3X_H
24#define LIBOPENCM3_PMC_COMMON_3A3U3X_H
25
26
27/* --- Power Management Controller (PMC) registers ----------------------- */
28
29/* UTMI Clock Register */
30#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
31
32
33/* --- Register contents --------------------------------------------------- */
34
35
36/* --- PMC UTMI Clock Configuration Register (CKGR_UCKR) ------------------- */
37
38/* UTMI PLL Start-up Time */
39#define CKGR_UCKR_UPLLCOUNT_SHIFT 20
40#define CKGR_UCKR_UPLLCOUNT_MASK (0x0F << CKGR_UCKR_UPLLCOUNT_SHIFT)
41
42/* UTMI PLL Enable */
43#define CKGR_UCKR_UPLLEN (0x01 << 16)
44
45/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
46
47/* UPLL Divide by 2 */
48#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
49
50/* Master Clock Source Selection */
51#define PMC_MCKR_CSS_UPLL_CLK (3 << PMC_MCKR_CSS_SHIFT)
52
53
54/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
55
56/* Master Clock Source Selection */
57#define PMC_PCK0_CSS_UPLL_CLK (3 << PMC_PCK0_CSS_SHIFT)
58
59
60/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
61
62/* Master Clock Source Selection */
63#define PMC_PCK1_CSS_UPLL_CLK (3 << PMC_PCK1_CSS_SHIFT)
64
65
66/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
67
68/* Master Clock Source Selection */
69#define PMC_PCK2_CSS_UPLL_CLK (3 << PMC_PCK2_CSS_SHIFT)
70
71
72/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
73
74/* UTMI PLL Lock Interrupt Enable */
75#define PMC_IER_LOCKU (0x01 << 6)
76
77
78/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
79
80/* UTMI PLL Lock Interrupt Disable */
81#define PMC_IDR_LOCKU (0x01 << 6)
82
83
84/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
85
86/* UTMI PLL Lock Status */
87#define PMC_SR_LOCKU (0x01 << 6)
88
89
90/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */
91
92/* UTMI PLL Lock Interrupt Mask */
93#define PMC_IMR_LOCKU (0x01 << 6)
94
95
96#endif
97
98#else
99#warning "pmc_common_3a3u3x.h should not be included explicitly, only via pmc.h"
100#endif