sam/3a/vector_nvic.c

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/* This file is part of the libopencm3 project.
 *
 * It was generated by the irq2nvic_h script.
 *
 * This part needs to get included in the compilation unit where
 * blocking_handler gets defined due to the way #pragma works.
 */
 
 
/** @defgroup CM3_nvic_isrdecls_SAM3A User interrupt service routines (ISR) defaults for Atmel SAM3A series
    @ingroup CM3_nvic_isrdecls
 
    @{*/
 
void supc_isr(void) __attribute__((weak, alias("blocking_handler")));
void rstc_isr(void) __attribute__((weak, alias("blocking_handler")));
void rtc_isr(void) __attribute__((weak, alias("blocking_handler")));
void rtt_isr(void) __attribute__((weak, alias("blocking_handler")));
void wdt_isr(void) __attribute__((weak, alias("blocking_handler")));
void pmc_isr(void) __attribute__((weak, alias("blocking_handler")));
void eefc0_isr(void) __attribute__((weak, alias("blocking_handler")));
void eefc1_isr(void) __attribute__((weak, alias("blocking_handler")));
void uart_isr(void) __attribute__((weak, alias("blocking_handler")));
void smc_sdramc_isr(void) __attribute__((weak, alias("blocking_handler")));
void sdramc_isr(void) __attribute__((weak, alias("blocking_handler")));
void pioa_isr(void) __attribute__((weak, alias("blocking_handler")));
void piob_isr(void) __attribute__((weak, alias("blocking_handler")));
void pioc_isr(void) __attribute__((weak, alias("blocking_handler")));
void piod_isr(void) __attribute__((weak, alias("blocking_handler")));
void pioe_isr(void) __attribute__((weak, alias("blocking_handler")));
void piof_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart0_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart1_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart2_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart3_isr(void) __attribute__((weak, alias("blocking_handler")));
void hsmci_isr(void) __attribute__((weak, alias("blocking_handler")));
void twi0_isr(void) __attribute__((weak, alias("blocking_handler")));
void twi1_isr(void) __attribute__((weak, alias("blocking_handler")));
void spi0_isr(void) __attribute__((weak, alias("blocking_handler")));
void spi1_isr(void) __attribute__((weak, alias("blocking_handler")));
void ssc_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc0_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc1_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc2_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc3_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc4_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc5_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc6_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc7_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc8_isr(void) __attribute__((weak, alias("blocking_handler")));
void pwm_isr(void) __attribute__((weak, alias("blocking_handler")));
void adc_isr(void) __attribute__((weak, alias("blocking_handler")));
void dacc_isr(void) __attribute__((weak, alias("blocking_handler")));
void dmac_isr(void) __attribute__((weak, alias("blocking_handler")));
void uotghs_isr(void) __attribute__((weak, alias("blocking_handler")));
void trng_isr(void) __attribute__((weak, alias("blocking_handler")));
void reserved0_isr(void) __attribute__((weak, alias("blocking_handler")));
void can0_isr(void) __attribute__((weak, alias("blocking_handler")));
void can1_isr(void) __attribute__((weak, alias("blocking_handler")));
 
/**@}*/
 
/* Initialization template for the interrupt vector table. This definition is
 * used by the startup code generator (vector.c) to set the initial values for
 * the interrupt handling routines to the chip family specific _isr weak
 * symbols. */
 
#define IRQ_HANDLERS \
    [NVIC_SUPC_IRQ] = supc_isr, \
    [NVIC_RSTC_IRQ] = rstc_isr, \
    [NVIC_RTC_IRQ] = rtc_isr, \
    [NVIC_RTT_IRQ] = rtt_isr, \
    [NVIC_WDT_IRQ] = wdt_isr, \
    [NVIC_PMC_IRQ] = pmc_isr, \
    [NVIC_EEFC0_IRQ] = eefc0_isr, \
    [NVIC_EEFC1_IRQ] = eefc1_isr, \
    [NVIC_UART_IRQ] = uart_isr, \
    [NVIC_SMC_SDRAMC_IRQ] = smc_sdramc_isr, \
    [NVIC_SDRAMC_IRQ] = sdramc_isr, \
    [NVIC_PIOA_IRQ] = pioa_isr, \
    [NVIC_PIOB_IRQ] = piob_isr, \
    [NVIC_PIOC_IRQ] = pioc_isr, \
    [NVIC_PIOD_IRQ] = piod_isr, \
    [NVIC_PIOE_IRQ] = pioe_isr, \
    [NVIC_PIOF_IRQ] = piof_isr, \
    [NVIC_USART0_IRQ] = usart0_isr, \
    [NVIC_USART1_IRQ] = usart1_isr, \
    [NVIC_USART2_IRQ] = usart2_isr, \
    [NVIC_USART3_IRQ] = usart3_isr, \
    [NVIC_HSMCI_IRQ] = hsmci_isr, \
    [NVIC_TWI0_IRQ] = twi0_isr, \
    [NVIC_TWI1_IRQ] = twi1_isr, \
    [NVIC_SPI0_IRQ] = spi0_isr, \
    [NVIC_SPI1_IRQ] = spi1_isr, \
    [NVIC_SSC_IRQ] = ssc_isr, \
    [NVIC_TC0_IRQ] = tc0_isr, \
    [NVIC_TC1_IRQ] = tc1_isr, \
    [NVIC_TC2_IRQ] = tc2_isr, \
    [NVIC_TC3_IRQ] = tc3_isr, \
    [NVIC_TC4_IRQ] = tc4_isr, \
    [NVIC_TC5_IRQ] = tc5_isr, \
    [NVIC_TC6_IRQ] = tc6_isr, \
    [NVIC_TC7_IRQ] = tc7_isr, \
    [NVIC_TC8_IRQ] = tc8_isr, \
    [NVIC_PWM_IRQ] = pwm_isr, \
    [NVIC_ADC_IRQ] = adc_isr, \
    [NVIC_DACC_IRQ] = dacc_isr, \
    [NVIC_DMAC_IRQ] = dmac_isr, \
    [NVIC_UOTGHS_IRQ] = uotghs_isr, \
    [NVIC_TRNG_IRQ] = trng_isr, \
    [NVIC_RESERVED0_IRQ] = reserved0_isr, \
    [NVIC_CAN0_IRQ] = can0_isr, \
    [NVIC_CAN1_IRQ] = can1_isr