sam/3s/vector_nvic.c

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/* This file is part of the libopencm3 project.
 *
 * It was generated by the irq2nvic_h script.
 *
 * This part needs to get included in the compilation unit where
 * blocking_handler gets defined due to the way #pragma works.
 */
 
 
/** @defgroup CM3_nvic_isrdecls_SAM3S User interrupt service routines (ISR) defaults for Atmel SAM3S series
    @ingroup CM3_nvic_isrdecls
 
    @{*/
 
void supc_isr(void) __attribute__((weak, alias("blocking_handler")));
void rstc_isr(void) __attribute__((weak, alias("blocking_handler")));
void rtc_isr(void) __attribute__((weak, alias("blocking_handler")));
void rtt_isr(void) __attribute__((weak, alias("blocking_handler")));
void wdt_isr(void) __attribute__((weak, alias("blocking_handler")));
void pmc_isr(void) __attribute__((weak, alias("blocking_handler")));
void eefc_isr(void) __attribute__((weak, alias("blocking_handler")));
void reserved0_isr(void) __attribute__((weak, alias("blocking_handler")));
void uart0_isr(void) __attribute__((weak, alias("blocking_handler")));
void uart1_isr(void) __attribute__((weak, alias("blocking_handler")));
void smc_isr(void) __attribute__((weak, alias("blocking_handler")));
void pioa_isr(void) __attribute__((weak, alias("blocking_handler")));
void piob_isr(void) __attribute__((weak, alias("blocking_handler")));
void pioc_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart0_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart1_isr(void) __attribute__((weak, alias("blocking_handler")));
void usart2_isr(void) __attribute__((weak, alias("blocking_handler")));
void reserved1_isr(void) __attribute__((weak, alias("blocking_handler")));
void hsmci_isr(void) __attribute__((weak, alias("blocking_handler")));
void twi0_isr(void) __attribute__((weak, alias("blocking_handler")));
void twi1_isr(void) __attribute__((weak, alias("blocking_handler")));
void spi_isr(void) __attribute__((weak, alias("blocking_handler")));
void ssc_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc0_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc1_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc2_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc3_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc4_isr(void) __attribute__((weak, alias("blocking_handler")));
void tc5_isr(void) __attribute__((weak, alias("blocking_handler")));
void adc_isr(void) __attribute__((weak, alias("blocking_handler")));
void dacc_isr(void) __attribute__((weak, alias("blocking_handler")));
void pwm_isr(void) __attribute__((weak, alias("blocking_handler")));
void crccu_isr(void) __attribute__((weak, alias("blocking_handler")));
void acc_isr(void) __attribute__((weak, alias("blocking_handler")));
void udp_isr(void) __attribute__((weak, alias("blocking_handler")));
 
/**@}*/
 
/* Initialization template for the interrupt vector table. This definition is
 * used by the startup code generator (vector.c) to set the initial values for
 * the interrupt handling routines to the chip family specific _isr weak
 * symbols. */
 
#define IRQ_HANDLERS \
    [NVIC_SUPC_IRQ] = supc_isr, \
    [NVIC_RSTC_IRQ] = rstc_isr, \
    [NVIC_RTC_IRQ] = rtc_isr, \
    [NVIC_RTT_IRQ] = rtt_isr, \
    [NVIC_WDT_IRQ] = wdt_isr, \
    [NVIC_PMC_IRQ] = pmc_isr, \
    [NVIC_EEFC_IRQ] = eefc_isr, \
    [NVIC_RESERVED0_IRQ] = reserved0_isr, \
    [NVIC_UART0_IRQ] = uart0_isr, \
    [NVIC_UART1_IRQ] = uart1_isr, \
    [NVIC_SMC_IRQ] = smc_isr, \
    [NVIC_PIOA_IRQ] = pioa_isr, \
    [NVIC_PIOB_IRQ] = piob_isr, \
    [NVIC_PIOC_IRQ] = pioc_isr, \
    [NVIC_USART0_IRQ] = usart0_isr, \
    [NVIC_USART1_IRQ] = usart1_isr, \
    [NVIC_USART2_IRQ] = usart2_isr, \
    [NVIC_RESERVED1_IRQ] = reserved1_isr, \
    [NVIC_HSMCI_IRQ] = hsmci_isr, \
    [NVIC_TWI0_IRQ] = twi0_isr, \
    [NVIC_TWI1_IRQ] = twi1_isr, \
    [NVIC_SPI_IRQ] = spi_isr, \
    [NVIC_SSC_IRQ] = ssc_isr, \
    [NVIC_TC0_IRQ] = tc0_isr, \
    [NVIC_TC1_IRQ] = tc1_isr, \
    [NVIC_TC2_IRQ] = tc2_isr, \
    [NVIC_TC3_IRQ] = tc3_isr, \
    [NVIC_TC4_IRQ] = tc4_isr, \
    [NVIC_TC5_IRQ] = tc5_isr, \
    [NVIC_ADC_IRQ] = adc_isr, \
    [NVIC_DACC_IRQ] = dacc_isr, \
    [NVIC_PWM_IRQ] = pwm_isr, \
    [NVIC_CRCCU_IRQ] = crccu_isr, \
    [NVIC_ACC_IRQ] = acc_isr, \
    [NVIC_UDP_IRQ] = udp_isr