libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
sam/3u/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
5 * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef SAM3U_MEMORYMAP_H
22#define SAM3U_MEMORYMAP_H
23
24#include <libopencm3/cm3/common.h>
25
26/* --- SAM3U peripheral space -------------------------------------------- */
27#define HSMCI_BASE (0x40000000U)
28#define SSC_BASE (0x40004000U)
29#define SPI_BASE (0x40008000U)
30#define TC0_BASE (0x40080000U)
31#define TC1_BASE (0x40080040U)
32#define TC2_BASE (0x40080080U)
33#define TWI0_BASE (0x40084000U)
34#define TWI1_BASE (0x40088000U)
35#define PWM_BASE (0x4008C000U)
36#define USART0_BASE (0x40090000U)
37#define USART1_BASE (0x40094000U)
38#define USART2_BASE (0x40098000U)
39#define USART3_BASE (0x4009C000U)
40#define UDPHS_BASE (0x400A4000U)
41#define ADC12B_BASE (0x400A8000U)
42#define ADC_BASE (0x400AC000U)
43#define DMAC_BASE (0x400B0000U)
44
45/* --- SAM3U system controller space ------------------------------------- */
46#define SMC_BASE (0x400E0000U)
47#define MATRIX_BASE (0x400E0200U)
48#define PMC_BASE (0x400E0400U)
49#define UART_BASE (0x400E0600U)
50#define CHIPID_BASE (0x400E0740U)
51#define EEFC0_BASE (0x400E0800U)
52#define EEFC1_BASE (0x400E0A00U)
53#define PIOA_BASE (0x400E0C00U)
54#define PIOB_BASE (0x400E0E00U)
55#define PIOC_BASE (0x400E1000U)
56#define RSTC_BASE (0x400E1200U)
57#define SUPC_BASE (0x400E1210U)
58#define RTT_BASE (0x400E1230U)
59#define WDT_BASE (0x400E1250U)
60#define RTC_BASE (0x400E1260U)
61#define GPBR_BASE (0x400E1290U)
62
63#endif