libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/f2/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_MEMORYMAP_H
21#define LIBOPENCM3_MEMORYMAP_H
22
24
25/* --- STM32F20x specific peripheral definitions --------------------------- */
26
27/* Memory map for all busses */
28#define FLASH_BASE (0x08000000U)
29#define PERIPH_BASE (0x40000000U)
30#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
31#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
32#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
33#define PERIPH_BASE_AHB2 (0x50000000U)
34#define PERIPH_BASE_AHB3 (0x60000000U)
35
36/* Register boundary addresses */
37
38/* APB1 */
39#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
40#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
41#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
42#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
43#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
44#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
45#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
46#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
47#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
48/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
49#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
50#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
51#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
52/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
53#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
54#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
55/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
56#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
57#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
58#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
59#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
60#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
61#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
62#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
63/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */
64#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
65#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
66/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
67#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
68#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
69/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
70
71/* APB2 */
72#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
73#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
74/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
75#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
76#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
77/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
78#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
79#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
80#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
81/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
82#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)
83/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
84#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
85/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */
86#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
87#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
88#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
89#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
90#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
91/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */
92
93/* AHB1 */
94#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
95#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
96#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
97#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
98#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
99#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
100#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
101#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
102#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
103/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
104#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
105/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
106#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
107#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
108#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
109/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
110#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
111#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
112/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
113#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
114/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */
115#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
116/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
117
118/* AHB2 */
119#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000)
120/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
121#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
122/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
123#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
124#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
125#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
126/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
127
128/* AHB3 */
129#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000)
130
131/* PPIB */
132#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
133
134/* Device Electronic Signature */
135#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U)
136#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U)
137#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
138#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
139#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
140
141
142#endif