libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
comparator.h
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1/** @defgroup comp_defines COMP Defines
2 *
3 * @brief <b>libopencm3 Defined Constants and Types for the STM32F3xx
4 * Comparator module</b>
5 *
6 * @ingroup STM32F3xx_defines
7 *
8 * @version 1.0.0
9 *
10 * @date 20 Jul 2018
11 *
12 *LGPL License Terms @ref lgpl_license
13 */
14/*
15 * This file is part of the libopencm3 project.
16 *
17 * This library is free software: you can redistribute it and/or modify
18 * it under the terms of the GNU Lesser General Public License as published by
19 * the Free Software Foundation, either version 3 of the License, or
20 * (at your option) any later version.
21 *
22 * This library is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU Lesser General Public License for more details.
26 *
27 * You should have received a copy of the GNU Lesser General Public License
28 * along with this library. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31#ifndef LIBOPENCM3_COMP_H
32#define LIBOPENCM3_COMP_H
33/**@{*/
34
35#define COMP1 (COMP_BASE + 0x1C)
36#define COMP2 (COMP_BASE + 0x20)
37#define COMP3 (COMP_BASE + 0x24)
38#define COMP4 (COMP_BASE + 0x28)
39#define COMP5 (COMP_BASE + 0x2C)
40#define COMP6 (COMP_BASE + 0x30)
41#define COMP7 (COMP_BASE + 0x34)
42
43/* Comparator registers */
44
45/* Control and status register (COMPx_CSR) */
46#define COMP_CSR(comp_base) MMIO32((comp_base) + 0x00)
47#define COMP1_CSR COMP_CSR(COMP1)
48#define COMP2_CSR COMP_CSR(COMP2)
49#define COMP3_CSR COMP_CSR(COMP3)
50#define COMP4_CSR COMP_CSR(COMP4)
51#define COMP5_CSR COMP_CSR(COMP5)
52#define COMP6_CSR COMP_CSR(COMP6)
53#define COMP7_CSR COMP_CSR(COMP7)
54
55/* COMPx_CSR values */
56
57#define COMP_CSR_LOCK (0x1 << 31)
58#define COMP_CSR_OUT (0x1 << 30)
59
60/* individual blanking sources depends on COMP used */
61#define COMP_CSR_BLANKING_MASK (0x7)
62#define COMP_CSR_BLANKING_SHIFT (18)
63#define COMP_CSR_BLANKING_NONE (0x0)
64#define COMP_CSR_BLANKING(blanking) (((blanking) & COMP_CSR_BLANKING_MASK) << COMP_CSR_BLANKING_SHIFT)
65
66/* only on COMP1/3/5/7 */
67#define COMP_CSR_HYST_NONE (0x0)
68#define COMP_CSR_HYST_LOW (0x1)
69#define COMP_CSR_HYST_MEDIUM (0x2)
70#define COMP_CSR_HYST_HIGH (0x3)
71#define COMP_CSR_HYST_MASK (0x3)
72#define COMP_CSR_HYST_SHIFT (16)
73
74#define COMP_CSR_POL (0x1 << 15)
75
76/* individual value depends on COMP used */
77#define COMP_CSR_OUTSEL(outsel) (((outsel) & COMP_CSR_OUTSEL_MASK) << COMP_CSR_OUTSEL_SHIFT)
78#define COMP_CSR_OUTSEL_MASK (0xf)
79#define COMP_CSR_OUTSEL_SHIFT (10)
80
81/* only on COMP2/4/6 */
82#define COMP_CSR_WINMODE (0x1 << 9)
83
84/* not available on COMP1 */
85#define COMP_CSR_INPSEL (0x1 << 7)
86
87/* individual value depends on COMP used,
88 also respects bit 3 (INMSEL[3]) where available */
89#define COMP_CSR_INMSEL(inmsel) ((((inmsel) & 0x7) << 4) | \
90 ((((inmsel) & 0x8) >> 3) << 22))
91#define COMP_CSR_INMSEL_MASK (0x7 << 4)
92
93#define COMP_CSR_MODE_HIGHSPEED (0x0)
94#define COMP_CSR_MODE_MEDIUMSPEED (0x1)
95#define COMP_CSR_MODE_LOWSPEED (0x2)
96#define COMP_CSR_MODE_ULTRALOWPOWER (0x3)
97#define COMP_CSR_MODE_MASK (0x3)
98#define COMP_CSR_MODE_SHIFT (2)
99
100/* only on COMP1 and COMP2 */
101#define COMP_CSR_INPDAC (0x1 << 1)
102
103#define COMP_CSR_EN (0x1 << 0)
104
105/**@}*/
106#endif