libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
dcmi_common_f47.h
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1/** @addtogroup dcmi_defines
2 *
3 * @version 1.0.0
4 *
5 * @author @htmlonly © @endhtmlonly 2020
6 * Smolyaninov Nikolay <smolin35@gmail.com>
7 * @author @htmlonly &copy; @endhtmlonly 2017
8 * Marek Koza <qyx@krtko.org>
9 *
10 * @date 15 May 2020
11 *
12 * This library supports the Digital camera interface (DCMI) in the STM32F4xx
13 * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
14 *
15 * LGPL License Terms @ref lgpl_license
16 */
17/*
18 * This file is part of the libopencm3 project.
19 *
20 * Copyright (C) 2020, Smolyaninov Nikolay <smolin35@gmail.com>
21 * Copyright (C) 2017, Marek Koza <qyx@krtko.org>
22 *
23 * This library is free software: you can redistribute it and/or modify
24 * it under the terms of the GNU Lesser General Public License as published by
25 * the Free Software Foundation, either version 3 of the License, or
26 * (at your option) any later version.
27 *
28 * This library is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU Lesser General Public License for more details.
32 *
33 * You should have received a copy of the GNU Lesser General Public License
34 * along with this library. If not, see <http://www.gnu.org/licenses/>.
35 */
36
37#pragma once
38
39#include <libopencm3/cm3/common.h>
40#include <libopencm3/stm32/memorymap.h>
41
42/**@{*/
43
44/**
45 * DCMI control register 1
46 */
47#define DCMI_CR MMIO32(DCMI_BASE + 0x0U)
48/**
49 * @defgroup dcmi_cr_values DCMI_CR Values
50 * @{
51 */
52#define DCMI_CR_EN (1 << 14)
53#define DCMI_CR_EDM1 (1 << 11)
54#define DCMI_CR_EDM0 (1 << 10)
55#define DCMI_CR_FCRC1 (1 << 9)
56#define DCMI_CR_FCRC0 (1 << 8)
57#define DCMI_CR_VSPOL (1 << 7)
58#define DCMI_CR_HSPOL (1 << 6)
59#define DCMI_CR_PCKPOL (1 << 5)
60#define DCMI_CR_ESS (1 << 4)
61#define DCMI_CR_JPEG (1 << 3)
62#define DCMI_CR_CROP (1 << 2)
63#define DCMI_CR_CM (1 << 1)
64#define DCMI_CR_CAPTURE (1 << 0)
65/**@}*/
66
67/**
68 * DCMI status register
69 */
70#define DCMI_SR MMIO32(DCMI_BASE + 0x04U)
71/**
72 * @defgroup dcmi_sr_values DCMI_SR Values
73 * @{
74 */
75#define DCMI_SR_FNE (1 << 2)
76#define DCMI_SR_VSYNCK (1 << 1)
77#define DCMI_SR_HSYNCK (1 << 0)
78/**@}*/
79
80/**
81 * DCMI raw interrupt status register
82 *
83 * DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this
84 * register returns the status of the corresponding interrupt before masking with the DCMI_IER
85 * register value.
86 */
87#define DCMI_RIS MMIO32(DCMI_BASE + 0x08U)
88/**
89 * @defgroup dcmi_ris_values DCMI_RIS Values
90 * @{
91 */
92#define DCMI_RIS_LINE (1 << 4)
93#define DCMI_RIS_VSYNC (1 << 3)
94#define DCMI_RIS_ERR (1 << 2)
95#define DCMI_RIS_OVR (1 << 1)
96#define DCMI_RIS_FRAME (1 << 0)
97/**@}*/
98
99/**
100 * DCMI interrupt enable register
101 *
102 * The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set,
103 * the corresponding interrupt is enabled. This register is accessible in both read and write.
104 */
105#define DCMI_IER MMIO32(DCMI_BASE + 0x0CU)
106/**
107 * @defgroup dcmi_ier_values DCMI_IER Values
108 * @{
109 */
110#define DCMI_IER_LINE (1 << 4)
111#define DCMI_IER_VSYNC (1 << 3)
112#define DCMI_IER_ERR (1 << 2)
113#define DCMI_IER_OVR (1 << 1)
114#define DCMI_IER_FRAME (1 << 0)
115/**@}*/
116
117/**
118 * DCMI masked interrupt status register
119 *
120 * This DCMI_MIS register is a read-only register. When read, it returns the current masked
121 * status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in
122 * this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding
123 * bit in DCMI_RIS is set.
124 */
125#define DCMI_MIS MMIO32(DCMI_BASE + 0x10U)
126/**
127 * @defgroup dcmi_mis_values DCMI_MIS Values
128 * @{
129 */
130#define DCMI_MIS_LINE (1 << 4)
131#define DCMI_MIS_VSYNC (1 << 3)
132#define DCMI_MIS_ERR (1 << 2)
133#define DCMI_MIS_OVR (1 << 1)
134#define DCMI_MIS_FRAME (1 << 0)
135/**@}*/
136
137/**
138 * DCMI interrupt clear register
139 *
140 * The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the
141 * corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
142 */
143#define DCMI_ICR MMIO32(DCMI_BASE + 0x14U)
144/**
145 * @defgroup dcmi_icr_values DCMI_ICR Values
146 * @{
147 */
148#define DCMI_ICR_LINE (1 << 4)
149#define DCMI_ICR_VSYNC (1 << 3)
150#define DCMI_ICR_ERR (1 << 2)
151#define DCMI_ICR_OVR (1 << 1)
152#define DCMI_ICR_FRAME (1 << 0)
153/**@}*/
154
155/**
156 * DCMI embedded synchronization code register
157 */
158#define DCMI_ESCR MMIO32(DCMI_BASE + 0x18U)
159/**
160 * @defgroup dcmi_escr_values DCMI_ESCR Values
161 * @{
162 */
163#define DCMI_ESCR_FEC_SHIFT 24
164#define DCMI_ESCR_FEC_MASK 0xff
165#define DCMI_ESCR_LEC_SHIFT 16
166#define DCMI_ESCR_LEC_MASK 0xff
167#define DCMI_ESCR_LSC_SHIFT 8
168#define DCMI_ESCR_LSC_MASK 0xff
169#define DCMI_ESCR_FSC_SHIFT 0
170#define DCMI_ESCR_FSC_MASK 0xff
171/**@}*/
172
173
174/**
175 * DCMI embedded synchronization unmask register
176 */
177#define DCMI_ESUR MMIO32(DCMI_BASE + 0x1CU)
178/**
179 * @defgroup dcmi_esur_values DCMI_ESUR Values
180 * @{
181 */
182#define DCMI_ESUR_FEU_SHIFT 24
183#define DCMI_ESUR_FEU_MASK 0xff
184#define DCMI_ESUR_LEU_SHIFT 16
185#define DCMI_ESUR_LEU_MASK 0xff
186#define DCMI_ESUR_LSU_SHIFT 8
187#define DCMI_ESUR_LSU_MASK 0xff
188#define DCMI_ESUR_FSU_SHIFT 0
189#define DCMI_ESUR_FSU_MASK 0xff
190/**@}*/
191
192/**
193 * DCMI crop window start
194 */
195#define DCMI_CWSTRT MMIO32(DCMI_BASE + 0x20U)
196/**
197 * @defgroup dcmi_cwstrt_values DCMI_CWSTRT Values
198 * @{
199 */
200#define DCMI_CWSTRT_VST_SHIFT 16
201#define DCMI_CWSTRT_VST_MASK 0x1fff
202#define DCMI_CWSTRT_HOFFCNT_SHIFT 0
203#define DCMI_CWSTRT_HOFFCNT_MASK 0x3fff
204/**@}*/
205
206/**
207 * DCMI crop window size
208 */
209#define DCMI_CWSIZE MMIO32(DCMI_BASE + 0x24U)
210/**
211 * @defgroup dcmi_cwsize_values DCMI_CWSIZE Values
212 * @{
213 */
214#define DCMI_CWSIZE_VLINE_SHIFT 16
215#define DCMI_CWSIZE_VLINE_MASK 0x3fff
216#define DCMI_CWSIZE_CAPCNT_SHIFT 0
217#define DCMI_CWSIZE_CAPCNT_MASK 0x3fff
218/**@}*/
219
220/**
221 * DCMI data register
222 *
223 * The digital camera Interface packages all the received data in 32-bit format before
224 * requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA
225 * transfers and avoid DMA overrun conditions.
226 */
227#define DCMI_DR MMIO32(DCMI_BASE + 0x28U)
228
229/**@}*/