libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
fsmc.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_FSMC_H
21#define LIBOPENCM3_FSMC_H
22
23#include <libopencm3/cm3/common.h>
24#include <libopencm3/stm32/memorymap.h>
25
26#if defined(STM32F4)
27# include <libopencm3/stm32/f4/fmc.h>
28#elif defined(STM32F7)
29# include <libopencm3/stm32/f7/fmc.h>
30#elif defined(STM32H7)
31# include <libopencm3/stm32/h7/fmc.h>
32#endif
33
34/* --- Convenience macros -------------------------------------------------- */
35#define FSMC_BANK1_BASE 0x60000000U /* NOR / PSRAM */
36#define FSMC_BANK2_BASE 0x70000000U /* NAND flash (reserved in F7) */
37#define FSMC_BANK3_BASE 0x80000000U /* NAND flash */
38#define FSMC_BANK4_BASE 0x90000000U /* PC card (reserved in F7) */
39
40/* --- FSMC registers ------------------------------------------------------ */
41
42/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */
43#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * (x))
44#define FSMC_BCR1 FSMC_BCR(0)
45#define FSMC_BCR2 FSMC_BCR(1)
46#define FSMC_BCR3 FSMC_BCR(2)
47#define FSMC_BCR4 FSMC_BCR(3)
48
49/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */
50#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * (x))
51#define FSMC_BTR1 FSMC_BTR(0)
52#define FSMC_BTR2 FSMC_BTR(1)
53#define FSMC_BTR3 FSMC_BTR(2)
54#define FSMC_BTR4 FSMC_BTR(3)
55
56/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */
57#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * (x))
58#define FSMC_BWTR1 FSMC_BWTR(0)
59#define FSMC_BWTR2 FSMC_BWTR(1)
60#define FSMC_BWTR3 FSMC_BWTR(2)
61#define FSMC_BWTR4 FSMC_BWTR(3)
62
63/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */
64#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * (x))
65#define FSMC_PCR2 FSMC_PCR(1)
66#define FSMC_PCR3 FSMC_PCR(2)
67#define FSMC_PCR4 FSMC_PCR(3)
68
69/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */
70#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * (x))
71#define FSMC_SR2 FSMC_SR(1)
72#define FSMC_SR3 FSMC_SR(2)
73#define FSMC_SR4 FSMC_SR(3)
74
75/* Common memory space timing registers 2..4 (FSMC_PMEMx) */
76#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * (x))
77#define FSMC_PMEM2 FSMC_PMEM(1)
78#define FSMC_PMEM3 FSMC_PMEM(2)
79#define FSMC_PMEM4 FSMC_PMEM(3)
80
81/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */
82#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * (x))
83#define FSMC_PATT2 FSMC_PATT(1)
84#define FSMC_PATT3 FSMC_PATT(2)
85#define FSMC_PATT4 FSMC_PATT(3)
86
87/* I/O space timing register 4 (FSMC_PIO4) */
88#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0)
89
90/* ECC result registers 2/3 (FSMC_ECCRx) */
91#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * (x))
92#define FSMC_ECCR2 FSMC_ECCR(1)
93#define FSMC_ECCR3 FSMC_ECCR(2)
94
95/* --- FSMC_BCRx values ---------------------------------------------------- */
96
97/* Bits [31:20]: Reserved. */
98
99/* CBURSTRW: Write burst enable */
100#define FSMC_BCR_CBURSTRW (1 << 19)
101
102/* Bits [18:16]: Reserved. */
103
104/* ASYNCWAIT: Wait signal during asynchronous transfers */
105#define FSMC_BCR_ASYNCWAIT (1 << 15)
106
107/* EXTMOD: Extended mode enable */
108#define FSMC_BCR_EXTMOD (1 << 14)
109
110/* WAITEN: Wait enable bit */
111#define FSMC_BCR_WAITEN (1 << 13)
112
113/* WREN: Write enable bit */
114#define FSMC_BCR_WREN (1 << 12)
115
116/* WAITCFG: Wait timing configuration */
117#define FSMC_BCR_WAITCFG (1 << 11)
118
119/* WRAPMOD: Wrapped burst mode support */
120#define FSMC_BCR_WRAPMOD (1 << 10)
121
122/* WAITPOL: Wait signal polarity bit */
123#define FSMC_BCR_WAITPOL (1 << 9)
124
125/* BURSTEN: Burst enable bit */
126#define FSMC_BCR_BURSTEN (1 << 8)
127
128/* Bit 7: Reserved. */
129
130/* FACCEN: Flash access enable */
131#define FSMC_BCR_FACCEN (1 << 6)
132
133/* MWID[5:4]: Memory data bus width */
134#define FSMC_BCR_MWID (1 << 4)
135
136/* MTYP[3:2]: Memory type */
137#define FSMC_BCR_MTYP (1 << 2)
138
139/* MUXEN: Address/data multiplexing enable bit */
140#define FSMC_BCR_MUXEN (1 << 1)
141
142/* MBKEN: Memory bank enable bit */
143#define FSMC_BCR_MBKEN (1 << 0)
144
145/* --- FSMC_BTRx values ---------------------------------------------------- */
146
147/* Bits [31:30]: Reserved. */
148
149/* Same for read and write */
150#define FSMC_BTx_ACCMOD_A (0)
151#define FSMC_BTx_ACCMOD_B (1)
152#define FSMC_BTx_ACCMOD_C (2)
153#define FSMC_BTx_ACCMOD_D (3)
154
155/* ACCMOD[29:28]: Access mode */
156#define FSMC_BTR_ACCMOD (1 << 28)
157#define FSMC_BTR_ACCMODx(x) (((x) & 0x03) << 28)
158
159/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */
160#define FSMC_BTR_DATLAT (1 << 24)
161#define FSMC_BTR_DATLATx(x) (((x) & 0x0f) << 24)
162
163/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
164#define FSMC_BTR_CLKDIV (1 << 20)
165#define FSMC_BTR_CLKDIVx(x) (((x) & 0x0f) << 20)
166
167/* BUSTURN[19:16]: Bus turnaround phase duration */
168#define FSMC_BTR_BUSTURN (1 << 16)
169#define FSMC_BTR_BUSTURNx(x) (((x) & 0x0f) << 16)
170
171/* DATAST[15:8]: Data-phase duration */
172#define FSMC_BTR_DATAST (1 << 8)
173#define FSMC_BTR_DATASTx(x) (((x) & 0xff) << 8)
174
175/* ADDHLD[7:4]: Address-hold phase duration */
176#define FSMC_BTR_ADDHLD (1 << 4)
177#define FSMC_BTR_ADDHLDx(x) (((x) & 0x0f) << 4)
178
179/* ADDSET[3:0]: Address setup phase duration */
180#define FSMC_BTR_ADDSET (1 << 0)
181#define FSMC_BTR_ADDSETx(x) (((x) & 0x0f) << 0)
182
183/* --- FSMC_BWTRx values --------------------------------------------------- */
184
185/* Bits [31:30]: Reserved. */
186
187/* ACCMOD[29:28]: Access mode */
188#define FSMC_BWTR_ACCMOD (1 << 28)
189
190/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */
191#define FSMC_BWTR_DATLAT (1 << 24)
192
193/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
194#define FSMC_BWTR_CLKDIV (1 << 20)
195
196/* Bits [19..16]: Reserved. */
197
198/* DATAST[15:8]: Data-phase duration */
199#define FSMC_BWTR_DATAST (1 << 8)
200
201/* ADDHLD[7:4]: Address-hold phase duration */
202#define FSMC_BWTR_ADDHLD (1 << 4)
203
204/* ADDSET[3:0]: Address setup phase duration */
205#define FSMC_BWTR_ADDSET (1 << 0)
206
207/* --- FSMC_PCRx values ---------------------------------------------------- */
208
209/* Bits [31:20]: Reserved. */
210
211/* ECCPS[19:17]: ECC page size */
212#define FSMC_PCR_ECCPS (1 << 17)
213
214/* TAR[16:13]: ALE to RE delay */
215#define FSMC_PCR_TAR (1 << 13)
216
217/* TCLR[12:9]: CLE to RE delay */
218#define FSMC_PCR_TCLR (1 << 9)
219
220/* Bits [8..7]: Reserved. */
221
222/* ECCEN: ECC computation logic enable bit */
223#define FSMC_PCR_ECCEN (1 << 6)
224
225/* PWID[5:4]: Databus width */
226#define FSMC_PCR_PWID (1 << 4)
227
228/* PTYP: Memory type */
229#define FSMC_PCR_PTYP (1 << 3)
230
231/* PBKEN: PC Card/NAND Flash memory bank enable bit */
232#define FSMC_PCR_PBKEN (1 << 2)
233
234/* PWAITEN: Wait feature enable bit */
235#define FSMC_PCR_PWAITEN (1 << 1)
236
237/* Bit 0: Reserved. */
238
239/* --- FSMC_SRx values ----------------------------------------------------- */
240
241/* Bits [31:7]: Reserved. */
242
243/* FEMPT: FIFO empty */
244#define FSMC_SR_FEMPT (1 << 6)
245
246/* IFEN: Interrupt falling edge detection enable bit */
247#define FSMC_SR_IFEN (1 << 5)
248
249/* ILEN: Interrupt high-level detection enable bit */
250#define FSMC_SR_ILEN (1 << 4)
251
252/* IREN: Interrupt rising edge detection enable bit */
253#define FSMC_SR_IREN (1 << 3)
254
255/* IFS: Interrupt falling edge status */
256#define FSMC_SR_IFS (1 << 2)
257
258/* ILS: Interrupt high-level status */
259#define FSMC_SR_ILS (1 << 1)
260
261/* IRS: Interrupt rising edge status */
262#define FSMC_SR_IRS (1 << 0)
263
264/* --- FSMC_PMEMx values --------------------------------------------------- */
265
266/* MEMHIZx[31:24]: Common memory x databus HiZ time */
267#define FSMC_PMEM_MEMHIZX (1 << 24)
268
269/* MEMHOLDx[23:16]: Common memory x hold time */
270#define FSMC_PMEM_MEMHOLDX (1 << 16)
271
272/* MEMWAITx[15:8]: Common memory x wait time */
273#define FSMC_PMEM_MEMWAITX (1 << 8)
274
275/* MEMSETx[7:0]: Common memory x setup time */
276#define FSMC_PMEM_MEMSETX (1 << 0)
277
278/* --- FSMC_PATTx values --------------------------------------------------- */
279
280/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */
281#define FSMC_PATT_ATTHIZX (1 << 24)
282
283/* ATTHOLDx[23:16]: Attribute memory x hold time */
284#define FSMC_PATT_ATTHOLDX (1 << 16)
285
286/* ATTWAITx[15:8]: Attribute memory x wait time */
287#define FSMC_PATT_ATTWAITX (1 << 8)
288
289/* ATTSETx[7:0]: Attribute memory x setup time */
290#define FSMC_PATT_ATTSETX (1 << 0)
291
292/* --- FSMC_PIO4 values ---------------------------------------------------- */
293
294/* IOHIZx[31:24]: I/O x databus HiZ time */
295#define FSMC_PIO4_IOHIZX (1 << 24)
296
297/* IOHOLDx[23:16]: I/O x hold time */
298#define FSMC_PIO4_IOHOLDX (1 << 16)
299
300/* IOWAITx[15:8]: I/O x wait time */
301#define FSMC_PIO4_IOWAITX (1 << 8)
302
303/* IOSETx[7:0]: I/O x setup time */
304#define FSMC_PIO4_IOSETX (1 << 0)
305
306/* --- FSMC_ECCRx values --------------------------------------------------- */
307
308/* ECCx[31:0]: ECC result */
309#define FSMC_ECCR_ECCX (1 << 0)
310
311#endif