libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
otg_hs.h
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file covers definitions for DesignWare USB OTG HS peripherals.
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*/
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#ifndef LIBOPENCM3_USB_DWC_OTG_HS_H
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#define LIBOPENCM3_USB_DWC_OTG_HS_H
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#include <
libopencm3/cm3/common.h
>
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#include <
libopencm3/usb/dwc/otg_common.h
>
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/* Memory map is required for USB_OTG_HS_BASE address */
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#if defined(STM32F2) || defined(STM32F4) || defined(STM32F7)
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# include <
libopencm3/stm32/memorymap.h
>
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#else
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# error "device family not supported by dwc/otg_hs."
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#endif
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/* OTG_HS specific registers */
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/* Host-mode Control and Status Registers */
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#define OTG_HCSPLT(x) (0x504 + 0x20*(x))
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#define OTG_HCDMA(x) (0x514 + 0x20*(x))
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/* Device-mode Control and Status Registers */
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#define OTG_DEACHHINT 0x838
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#define OTG_DEACHHINTMSK 0x83C
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#define OTG_DIEPEACHMSK1 0x844
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#define OTG_DOEPEACHMSK1 0x884
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#define OTG_DIEPDMA(x) (0x914 + 0x20*(x))
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#define OTG_DOEPDMA(x) (0xB14 + 0x20*(x))
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/***********************************************************************/
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/* Core Global Control and Status Registers */
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#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
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#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
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#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
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#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
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#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
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#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
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#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
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#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
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#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
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#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
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#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
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#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
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#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
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#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
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#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
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#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
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/* Host-mode Control and Status Registers */
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#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
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#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
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#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
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#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
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#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
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#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
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#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
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#define OTG_HS_HCCHAR(x) MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
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#define OTG_HS_HCSPLT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
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#define OTG_HS_HCINT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
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#define OTG_HS_HCINTMSK(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
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#define OTG_HS_HCTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
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#define OTG_HS_HCDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))
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/* Device-mode Control and Status Registers */
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#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
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#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
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#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
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#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
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#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
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#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
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#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
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#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
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#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
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#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
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#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
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#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
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#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
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#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
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#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
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#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
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#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
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#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
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#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
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OTG_DIEPTSIZ(x))
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#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
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#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
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OTG_DOEPTSIZ(x))
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#define OTG_HS_DEACHHINT MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
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#define OTG_HS_DEACHHINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
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#define OTG_HS_DIEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
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#define OTG_HS_DOEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
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#define OTG_HS_DIEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
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#define OTG_HS_DOEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))
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/* Power and clock gating control and status register */
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#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
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/* Data FIFO */
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#define OTG_HS_FIFO(x) (&MMIO32(USB_OTG_HS_BASE + OTG_FIFO(x)))
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/* Device-mode CSRs*/
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/* OTG device each endpoint interrupt register (OTG_DEACHINT) */
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/* Bits 31:18 - Reserved */
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#define OTG_DEACHHINT_OEP1INT (1 << 17)
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/* Bits 16:2 - Reserved */
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#define OTG_DEACHHINT_IEP1INT (1 << 1)
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/* Bit 0 - Reserved */
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/* OTG device each in endpoint-1 interrupt register (OTG_DIEPEACHMSK1) */
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/* Bits 31:14 - Reserved */
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#define OTG_DIEPEACHMSK1_NAKM (1 << 13)
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/* Bits 12:10 - Reserved */
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#define OTG_DIEPEACHMSK1_BIM (1 << 9)
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#define OTG_DIEPEACHMSK1_TXFURM (1 << 8)
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/* Bit 7 - Reserved */
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#define OTG_DIEPEACHMSK1_INEPNEM (1 << 6)
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#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5)
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#define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4)
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#define OTG_DIEPEACHMSK1_TOM (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_DIEPEACHMSK1_EPDM (1 << 1)
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#define OTG_DIEPEACHMSK1_XFRCM (1 << 0)
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/* OTG device each OUT endpoint-1 interrupt register (OTG_DOEPEACHMSK1) */
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/* Bits 31:15 - Reserved */
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#define OTG_DOEPEACHMSK1_NYETM (1 << 14)
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#define OTG_DOEPEACHMSK1_NAKM (1 << 13)
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#define OTG_DOEPEACHMSK1_BERRM (1 << 12)
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/* Bits 11:10 - Reserved */
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#define OTG_DOEPEACHMSK1_BIM (1 << 9)
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#define OTG_DOEPEACHMSK1_OPEM (1 << 8)
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/* Bits 7:3 - Reserved */
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#define OTG_DOEPEACHMSK1_AHBERRM (1 << 2)
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#define OTG_DOEPEACHMSK1_EPDM (1 << 1)
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#define OTG_DOEPEACHMSK1_XFRCM (1 << 0)
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/* Host-mode CSRs */
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/* OTG host channel-x split control register (OTG_HCSPLTx) */
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#define OTG_HCSPLT_SPLITEN (1 << 31)
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/* Bits 30:17 - Reserved */
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#define OTG_HCSPLT_COMPLSPLT (1 << 16)
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#define OTG_HCSPLT_XACTPOS_ALL (0x3 << 14)
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#define OTG_HCSPLT_XACTPOS_BEGIN (0x2 << 14)
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#define OTG_HCSPLT_XACTPOS_MID (0x0 << 14)
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#define OTG_HCSPLT_XACTPOS_END (0x1 << 14)
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#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7)
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#define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0)
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#endif
common.h
otg_common.h
memorymap.h
include
libopencm3
usb
dwc
otg_hs.h
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