libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
usart_common_f124.h
Go to the documentation of this file.
1
/** @addtogroup usart_defines
2
3
@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
4
5
*/
6
7
/*
8
* This file is part of the libopencm3 project.
9
*
10
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
11
*
12
* This library is free software: you can redistribute it and/or modify
13
* it under the terms of the GNU Lesser General Public License as published by
14
* the Free Software Foundation, either version 3 of the License, or
15
* (at your option) any later version.
16
*
17
* This library is distributed in the hope that it will be useful,
18
* but WITHOUT ANY WARRANTY; without even the implied warranty of
19
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20
* GNU Lesser General Public License for more details.
21
*
22
* You should have received a copy of the GNU Lesser General Public License
23
* along with this library. If not, see <http://www.gnu.org/licenses/>.
24
*/
25
26
/**@{*/
27
28
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
29
The order of header inclusion is important. usart.h includes the device
30
specific memorymap.h header before including this header file.*/
31
32
/** @cond */
33
#if defined(LIBOPENCM3_USART_H)
34
/** @endcond */
35
#ifndef LIBOPENCM3_USART_COMMON_F124_H
36
#define LIBOPENCM3_USART_COMMON_F124_H
37
38
#include <
libopencm3/stm32/common/usart_common_all.h
>
39
40
41
/** @defgroup usart_reg_base USART register base addresses
42
* Holds all the U(S)ART peripherals supported.
43
* @{
44
*/
45
#define USART1 USART1_BASE
46
#define USART2 USART2_BASE
47
#define USART3 USART3_BASE
48
#define UART4 UART4_BASE
49
#define UART5 UART5_BASE
50
/**@}*/
51
52
/* --- USART registers ----------------------------------------------------- */
53
54
/* Status register (USARTx_SR) */
55
#define USART_SR(usart_base) MMIO32((usart_base) + 0x00)
56
#define USART1_SR USART_SR(USART1_BASE)
57
#define USART2_SR USART_SR(USART2_BASE)
58
#define USART3_SR USART_SR(USART3_BASE)
59
#define UART4_SR USART_SR(UART4_BASE)
60
#define UART5_SR USART_SR(UART5_BASE)
61
62
/* Data register (USARTx_DR) */
63
#define USART_DR(usart_base) MMIO32((usart_base) + 0x04)
64
#define USART1_DR USART_DR(USART1_BASE)
65
#define USART2_DR USART_DR(USART2_BASE)
66
#define USART3_DR USART_DR(USART3_BASE)
67
#define UART4_DR USART_DR(UART4_BASE)
68
#define UART5_DR USART_DR(UART5_BASE)
69
70
/* Baud rate register (USARTx_BRR) */
71
#define USART_BRR(usart_base) MMIO32((usart_base) + 0x08)
72
#define USART1_BRR USART_BRR(USART1_BASE)
73
#define USART2_BRR USART_BRR(USART2_BASE)
74
#define USART3_BRR USART_BRR(USART3_BASE)
75
#define UART4_BRR USART_BRR(UART4_BASE)
76
#define UART5_BRR USART_BRR(UART5_BASE)
77
78
/* Control register 1 (USARTx_CR1) */
79
#define USART_CR1(usart_base) MMIO32((usart_base) + 0x0c)
80
#define USART1_CR1 USART_CR1(USART1_BASE)
81
#define USART2_CR1 USART_CR1(USART2_BASE)
82
#define USART3_CR1 USART_CR1(USART3_BASE)
83
#define UART4_CR1 USART_CR1(UART4_BASE)
84
#define UART5_CR1 USART_CR1(UART5_BASE)
85
86
/* Control register 2 (USARTx_CR2) */
87
#define USART_CR2(usart_base) MMIO32((usart_base) + 0x10)
88
#define USART1_CR2 USART_CR2(USART1_BASE)
89
#define USART2_CR2 USART_CR2(USART2_BASE)
90
#define USART3_CR2 USART_CR2(USART3_BASE)
91
#define UART4_CR2 USART_CR2(UART4_BASE)
92
#define UART5_CR2 USART_CR2(UART5_BASE)
93
94
/* Control register 3 (USARTx_CR3) */
95
#define USART_CR3(usart_base) MMIO32((usart_base) + 0x14)
96
#define USART1_CR3 USART_CR3(USART1_BASE)
97
#define USART2_CR3 USART_CR3(USART2_BASE)
98
#define USART3_CR3 USART_CR3(USART3_BASE)
99
#define UART4_CR3 USART_CR3(UART4_BASE)
100
#define UART5_CR3 USART_CR3(UART5_BASE)
101
102
/* Guard time and prescaler register (USARTx_GTPR) */
103
#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x18)
104
#define USART1_GTPR USART_GTPR(USART1_BASE)
105
#define USART2_GTPR USART_GTPR(USART2_BASE)
106
#define USART3_GTPR USART_GTPR(USART3_BASE)
107
#define UART4_GTPR USART_GTPR(UART4_BASE)
108
#define UART5_GTPR USART_GTPR(UART5_BASE)
109
110
/** @defgroup usart_convenience_flags U(S)ART convenience Flags
111
* @ingroup STM32F_usart_defines
112
* We define the "common" lower flag bits using a standard name,
113
* allowing them to be used regardless of which usart peripheral
114
* version you have.
115
* @{
116
*/
117
#define USART_FLAG_PE USART_SR_PE
118
#define USART_FLAG_FE USART_SR_FE
119
#define USART_FLAG_NF USART_SR_NF
120
#define USART_FLAG_ORE USART_SR_ORE
121
#define USART_FLAG_IDLE USART_SR_IDLE
122
#define USART_FLAG_RXNE USART_SR_RXNE
123
#define USART_FLAG_TC USART_SR_TC
124
#define USART_FLAG_TXE USART_SR_TXE
125
/**@}*/
126
127
/* --- USART_SR values ----------------------------------------------------- */
128
/****************************************************************************/
129
/** @defgroup usart_sr_flags USART Status register Flags
130
@ingroup STM32F_usart_defines
131
132
@{*/
133
134
/** CTS: CTS flag */
135
/** @note: undefined on UART4 and UART5 */
136
#define USART_SR_CTS (1 << 9)
137
138
/** LBD: LIN break detection flag */
139
#define USART_SR_LBD (1 << 8)
140
141
/** TXE: Transmit data buffer empty */
142
#define USART_SR_TXE (1 << 7)
143
144
/** TC: Transmission complete */
145
#define USART_SR_TC (1 << 6)
146
147
/** RXNE: Read data register not empty */
148
#define USART_SR_RXNE (1 << 5)
149
150
/** IDLE: Idle line detected */
151
#define USART_SR_IDLE (1 << 4)
152
153
/** ORE: Overrun error */
154
#define USART_SR_ORE (1 << 3)
155
156
/** NE: Noise error flag */
157
#define USART_SR_NE (1 << 2)
158
159
/** FE: Framing error */
160
#define USART_SR_FE (1 << 1)
161
162
/** PE: Parity error */
163
#define USART_SR_PE (1 << 0)
164
/**@}*/
165
166
/* --- USART_DR values ----------------------------------------------------- */
167
168
/* USART_DR[8:0]: DR[8:0]: Data value */
169
#define USART_DR_MASK 0x1FF
170
171
/* --- USART_BRR values ---------------------------------------------------- */
172
173
/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
174
#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
175
/* DIV_Fraction[3:0]: fraction of USARTDIV */
176
#define USART_BRR_DIV_FRACTION_MASK 0xF
177
178
/* --- USART_CR1 values ---------------------------------------------------- */
179
180
/* UE: USART enable */
181
#define USART_CR1_UE (1 << 13)
182
183
/* M: Word length */
184
#define USART_CR1_M (1 << 12)
185
186
/* WAKE: Wakeup method */
187
#define USART_CR1_WAKE (1 << 11)
188
189
/* PCE: Parity control enable */
190
#define USART_CR1_PCE (1 << 10)
191
192
/* PS: Parity selection */
193
#define USART_CR1_PS (1 << 9)
194
195
/* PEIE: PE interrupt enable */
196
#define USART_CR1_PEIE (1 << 8)
197
198
/* TXEIE: TXE interrupt enable */
199
#define USART_CR1_TXEIE (1 << 7)
200
201
/* TCIE: Transmission complete interrupt enable */
202
#define USART_CR1_TCIE (1 << 6)
203
204
/* RXNEIE: RXNE interrupt enable */
205
#define USART_CR1_RXNEIE (1 << 5)
206
207
/* IDLEIE: IDLE interrupt enable */
208
#define USART_CR1_IDLEIE (1 << 4)
209
210
/* TE: Transmitter enable */
211
#define USART_CR1_TE (1 << 3)
212
213
/* RE: Receiver enable */
214
#define USART_CR1_RE (1 << 2)
215
216
/* RWU: Receiver wakeup */
217
#define USART_CR1_RWU (1 << 1)
218
219
/* SBK: Send break */
220
#define USART_CR1_SBK (1 << 0)
221
222
/* --- USART_CR2 values ---------------------------------------------------- */
223
224
/* LINEN: LIN mode enable */
225
#define USART_CR2_LINEN (1 << 14)
226
227
/* CLKEN: Clock enable */
228
#define USART_CR2_CLKEN (1 << 11)
229
230
/* CPOL: Clock polarity */
231
#define USART_CR2_CPOL (1 << 10)
232
233
/* CPHA: Clock phase */
234
#define USART_CR2_CPHA (1 << 9)
235
236
/* LBCL: Last bit clock pulse */
237
#define USART_CR2_LBCL (1 << 8)
238
239
/* LBDIE: LIN break detection interrupt enable */
240
#define USART_CR2_LBDIE (1 << 6)
241
242
/* LBDL: LIN break detection length */
243
#define USART_CR2_LBDL (1 << 5)
244
245
/* ADD[3:0]: Address of the usart node */
246
#define USART_CR2_ADD_MASK 0xF
247
248
/* --- USART_CR3 values ---------------------------------------------------- */
249
250
/* CTSIE: CTS interrupt enable */
251
/* Note: N/A on UART4 & UART5 */
252
#define USART_CR3_CTSIE (1 << 10)
253
254
/* CTSE: CTS enable */
255
/* Note: N/A on UART4 & UART5 */
256
#define USART_CR3_CTSE (1 << 9)
257
258
/* RTSE: RTS enable */
259
/* Note: N/A on UART4 & UART5 */
260
#define USART_CR3_RTSE (1 << 8)
261
262
/* DMAT: DMA enable transmitter */
263
/* Note: N/A on UART5 */
264
#define USART_CR3_DMAT (1 << 7)
265
266
/* DMAR: DMA enable receiver */
267
/* Note: N/A on UART5 */
268
#define USART_CR3_DMAR (1 << 6)
269
270
/* SCEN: Smartcard mode enable */
271
/* Note: N/A on UART4 & UART5 */
272
#define USART_CR3_SCEN (1 << 5)
273
274
/* NACK: Smartcard NACK enable */
275
/* Note: N/A on UART4 & UART5 */
276
#define USART_CR3_NACK (1 << 4)
277
278
/* HDSEL: Half-duplex selection */
279
#define USART_CR3_HDSEL (1 << 3)
280
281
/* IRLP: IrDA low-power */
282
#define USART_CR3_IRLP (1 << 2)
283
284
/* IREN: IrDA mode enable */
285
#define USART_CR3_IREN (1 << 1)
286
287
/* EIE: Error interrupt enable */
288
#define USART_CR3_EIE (1 << 0)
289
290
/* --- USART_GTPR values --------------------------------------------------- */
291
292
/* GT[7:0]: Guard time value */
293
/* Note: N/A on UART4 & UART5 */
294
#define USART_GTPR_GT_MASK (0xFF << 8)
295
296
/* PSC[7:0]: Prescaler value */
297
/* Note: N/A on UART4/5 */
298
#define USART_GTPR_PSC_MASK 0xFF
299
300
/* TODO */
/* Note to Uwe: what needs to be done here? */
301
302
#endif
303
/** @cond */
304
#else
305
#warning "usart_common_all.h should not be included directly, only via usart.h"
306
#endif
307
/** @endcond */
308
/**@}*/
309
usart_common_all.h
include
libopencm3
stm32
common
usart_common_f124.h
Generated on Tue Mar 7 2023 16:11:41 for libopencm3 by
1.9.4
1.9.4 1.9.4