libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
cm3/nvic.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
5 * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
6 * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
7 *
8 * This library is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public License
19 * along with this library. If not, see <http://www.gnu.org/licenses/>.
20 */
21/** @defgroup CM3_nvic_defines Cortex-M NVIC Defines
22 *
23 * @brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
24 *
25 * @ingroup CM3_defines
26 *
27 * @version 1.0.0
28 *
29 * @author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
30 *
31 * @date 18 August 2012
32 *
33 * LGPL License Terms @ref lgpl_license
34 */
35/**@{*/
36
37#ifndef LIBOPENCM3_NVIC_H
38#define LIBOPENCM3_NVIC_H
39
42
43/** @defgroup nvic_registers NVIC Registers
44 * @{
45 */
46
47/** ISER: Interrupt Set Enable Registers
48 * @note 8 32bit Registers
49 * @note Single register on CM0
50 */
51#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \
52 ((iser_id) * 4))
53
54/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
55
56/** ICER: Interrupt Clear Enable Registers
57 * @note 8 32bit Registers
58 * @note Single register on CM0
59 */
60#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \
61 ((icer_id) * 4))
62
63/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
64
65/** ISPR: Interrupt Set Pending Registers
66 * @note 8 32bit Registers
67 * @note Single register on CM0
68 */
69#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \
70 ((ispr_id) * 4))
71
72/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
73
74/** ICPR: Interrupt Clear Pending Registers
75 * @note 8 32bit Registers
76 * @note Single register on CM0
77 */
78#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \
79 ((icpr_id) * 4))
80
81/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
82
83/* Those defined only on ARMv7 and above */
84#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
85/** IABR: Interrupt Active Bit Register
86 * @note 8 32bit Registers */
87#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \
88 ((iabr_id) * 4))
89#endif
90
91/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
92
93/** IPR: Interrupt Priority Registers
94 * @note 240 8bit Registers
95 * @note 32 8bit Registers on CM0, requires word access
96 */
97#if defined(__ARM_ARCH_6M__)
98#define NVIC_IPR32(ipr_id) MMIO32(NVIC_BASE + 0x300 + \
99 ((ipr_id) * 4))
100#else
101#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \
102 (ipr_id))
103#endif
104
105#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
106/** STIR: Software Trigger Interrupt Register */
107#define NVIC_STIR MMIO32(STIR_BASE)
108#endif
109
110/**@}*/
111
112/* --- IRQ channel numbers-------------------------------------------------- */
113
114/* Cortex M0, M3 and M4 System Interrupts */
115/** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts
116@ingroup CM3_nvic_defines
117
118IRQ numbers -3 and -6 to -9 are reserved
119@{*/
120#define NVIC_NMI_IRQ -14
121#define NVIC_HARD_FAULT_IRQ -13
122
123/* Those defined only on ARMv7 and above */
124#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
125#define NVIC_MEM_MANAGE_IRQ -12
126#define NVIC_BUS_FAULT_IRQ -11
127#define NVIC_USAGE_FAULT_IRQ -10
128#endif
129
130/* irq numbers -6 to -9 are reserved */
131#define NVIC_SV_CALL_IRQ -5
132
133/* Those defined only on ARMv7 and above */
134#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
135#define DEBUG_MONITOR_IRQ -4
136#endif
137
138/* irq number -3 reserved */
139#define NVIC_PENDSV_IRQ -2
140#define NVIC_SYSTICK_IRQ -1
141/**@}*/
142
143/* @note User interrupts are family specific and are defined in a family
144 * specific header file in the corresponding subfolder.
145 */
146
148
149/* --- NVIC functions ------------------------------------------------------ */
150
152
153void nvic_enable_irq(uint8_t irqn);
154void nvic_disable_irq(uint8_t irqn);
155uint8_t nvic_get_pending_irq(uint8_t irqn);
156void nvic_set_pending_irq(uint8_t irqn);
157void nvic_clear_pending_irq(uint8_t irqn);
158uint8_t nvic_get_irq_enabled(uint8_t irqn);
159void nvic_set_priority(uint8_t irqn, uint8_t priority);
160
161/* Those defined only on ARMv7 and above */
162#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
163uint8_t nvic_get_active_irq(uint8_t irqn);
164void nvic_generate_software_interrupt(uint16_t irqn);
165#endif
166
167void reset_handler(void);
168void nmi_handler(void);
173
174/* Those defined only on ARMv7 and above */
175#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
176void mem_manage_handler(void);
177void bus_fault_handler(void);
178void usage_fault_handler(void);
179void debug_monitor_handler(void);
180#endif
181
183
184/**@}*/
185
186#endif
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
uint8_t nvic_get_pending_irq(uint8_t irqn)
NVIC Return Pending Interrupt.
Definition: nvic.c:84
void nvic_set_pending_irq(uint8_t irqn)
NVIC Set Pending Interrupt.
Definition: nvic.c:98
void nvic_set_priority(uint8_t irqn, uint8_t priority)
NVIC Set Interrupt Priority.
Definition: nvic.c:152
void nvic_clear_pending_irq(uint8_t irqn)
NVIC Clear Pending Interrupt.
Definition: nvic.c:112
void pend_sv_handler(void)
void hard_fault_handler(void)
uint8_t nvic_get_irq_enabled(uint8_t irqn)
NVIC Return Enabled Interrupt.
Definition: nvic.c:126
void nmi_handler(void)
void reset_handler(void)
Definition: vector.c:62
void sv_call_handler(void)
void nvic_enable_irq(uint8_t irqn)
NVIC Enable Interrupt.
Definition: nvic.c:57
void nvic_disable_irq(uint8_t irqn)
NVIC Disable Interrupt.
Definition: nvic.c:70
void sys_tick_handler(void)