libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
dbgmcu.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_STM32_DBGMCU_H
21#define LIBOPENCM3_STM32_DBGMCU_H
22
23#include <libopencm3/cm3/common.h>
24#include <libopencm3/stm32/memorymap.h>
25
26/* --- DBGMCU registers ---------------------------------------------------- */
27
28/* Debug MCU IDCODE register (DBGMCU_IDCODE) */
29#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00)
30
31/* Debug MCU configuration register (DBGMCU_CR) */
32/* Note: Only 32bit access supported. */
33#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04)
34
35/* --- DBGMCU_IDCODE values ------------------------------------------------ */
36
37#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff
38#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000
39
40/* --- DBGMCU_CR values ---------------------------------------------------- */
41
42/* Bit 31: Reserved. */
43
44/* Bits [24:22]: Reserved, must be kept cleared. */
45
46/* Bits [4:3]: Reserved. */
47
48#define DBGMCU_CR_SLEEP 0x00000001
49#define DBGMCU_CR_STOP 0x00000002
50#define DBGMCU_CR_STANDBY 0x00000004
51#define DBGMCU_CR_TRACE_IOEN 0x00000020
52#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0
53#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000
54#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040
55#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080
56#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0
57#define DBGMCU_CR_IWDG_STOP 0x00000100
58#define DBGMCU_CR_WWDG_STOP 0x00000200
59#define DBGMCU_CR_TIM1_STOP 0x00000400
60#define DBGMCU_CR_TIM2_STOP 0x00000800
61#define DBGMCU_CR_TIM3_STOP 0x00001000
62#define DBGMCU_CR_TIM4_STOP 0x00002000
63#define DBGMCU_CR_CAN1_STOP 0x00004000
64#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000
65#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000
66#define DBGMCU_CR_TIM8_STOP 0x00020000
67#define DBGMCU_CR_TIM5_STOP 0x00040000
68#define DBGMCU_CR_TIM6_STOP 0x00080000
69#define DBGMCU_CR_TIM7_STOP 0x00100000
70#define DBGMCU_CR_CAN2_STOP 0x00200000
71
72#endif