libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
tpiu.h
Go to the documentation of this file.
1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_CM3_TPIU_H
21#define LIBOPENCM3_CM3_TPIU_H
22
23/**
24 * @defgroup cm_tpiu Cortex-M Trace Port Interface Unit (TPIU)
25 * @ingroup CM3_defines
26 * @{
27 */
28
29/* Those defined only on ARMv7 and above */
30#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
31#error "Trace Port Interface Unit not available in CM0"
32#endif
33
34/* --- TPIU registers ------------------------------------------------------ */
35
36/* Supported Synchronous Port Size (TPIU_SSPSR) */
37#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
38
39/* Current Synchronous Port Size (TPIU_CSPSR) */
40#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
41
42/* Asynchronous Clock Prescaler (TPIU_ACPR) */
43#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
44
45/* Selected Pin Protocol (TPIU_SPPR) */
46#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
47
48/* Formatter and Flush Status Register (TPIU_FFSR) */
49#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
50
51/* Formatter and Flush Control Register (TPIU_FFCR) */
52#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
53
54/* (TPIU_DEVID) */
55#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
56
57/* CoreSight Lock Status Register for this peripheral */
58#define TPIU_LSR MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET)
59/* CoreSight Lock Access Register for this peripheral */
60#define TPIU_LAR MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET)
61
62/* TODO: PID, CID */
63
64/* --- TPIU_ACPR values ---------------------------------------------------- */
65
66/* Bits 31:16 - Reserved */
67/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
68
69/* --- TPIU_SPPR values ---------------------------------------------------- */
70
71/* Bits 31:2 - Reserved */
72#define TPIU_SPPR_SYNC (0x0)
73#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
74#define TPIU_SPPR_ASYNC_NRZ (0x2)
75
76/* --- TPIU_FFSR values ---------------------------------------------------- */
77
78/* Bits 31:4 - Reserved */
79#define TPIU_FFSR_FTNONSTOP (1 << 3)
80#define TPIU_FFSR_TCPRESENT (1 << 2)
81#define TPIU_FFSR_FTSTOPPED (1 << 1)
82#define TPIU_FFSR_FLINPROG (1 << 0)
83
84/* --- TPIU_FFCR values ---------------------------------------------------- */
85
86/* Bits 31:9 - Reserved */
87#define TPIU_FFCR_TRIGIN (1 << 8)
88/* Bits 7:2 - Reserved */
89#define TPIU_FFCR_ENFCONT (1 << 1)
90/* Bit 0 - Reserved */
91
92/* --- TPIU_DEVID values ---------------------------------------------------- */
93/* Bits 31:16 - Reserved */
94/* Bits 15:12 - Implementation defined */
95#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
96#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
97/* Bit 9 - RAZ, indicated that trace data and clock are supported */
98#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
99/* Bits 5:0 - Implementation defined */
100
101/**@}*/
102
103#endif