libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
spi_common_v2.h
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1/** @addtogroup spi_defines
2 */
3
4/*
5 * This file is part of the libopencm3 project.
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
22The order of header inclusion is important. spi.h includes the device
23specific memorymap.h header before including this header file.*/
24
25/** @cond */
26#ifdef LIBOPENCM3_SPI_H
27/** @endcond */
28#pragma once
29
30/**@{*/
31
33
34#define SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c)
35#define SPI1_DR8 SPI_DR8(SPI1_BASE)
36#define SPI2_DR8 SPI_DR8(SPI2_BASE)
37#define SPI3_DR8 SPI_DR8(SPI3_BASE)
38
39/* CRCL: CRC Length */
40/****************************************************************************/
41/** @defgroup spi_crcl SPI crc length
42 * @ingroup spi_defines
43 *
44 * @{*/
45
46#define SPI_CR1_CRCL_8BIT (0 << 11)
47#define SPI_CR1_CRCL_16BIT (1 << 11)
48/**@}*/
49#define SPI_CR1_CRCL (1 << 11)
50
51/* --- SPI_CR2 values ------------------------------------------------------ */
52
53/* LDMA_TX: Last DMA transfer for transmission */
54#define SPI_CR2_LDMA_TX (1 << 14)
55
56/* LDMA_RX: Last DMA transfer for reception */
57#define SPI_CR2_LDMA_RX (1 << 13)
58
59/* FRXTH: FIFO reception threshold */
60#define SPI_CR2_FRXTH (1 << 12)
61
62/* FRF: Frame format */
63/* Note: Not used in I2S mode. */
64#define SPI_CR2_FRF (1 << 4)
65#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
66#define SPI_CR2_FRF_TI_MODE (1 << 4)
67
68/* DS: Data size */
69/****************************************************************************/
70/** @defgroup spi_ds SPI data size
71 * @ingroup spi_defines
72 *
73 * @{*/
74#define SPI_CR2_DS_4BIT (0x3 << 8)
75#define SPI_CR2_DS_5BIT (0x4 << 8)
76#define SPI_CR2_DS_6BIT (0x5 << 8)
77#define SPI_CR2_DS_7BIT (0x6 << 8)
78#define SPI_CR2_DS_8BIT (0x7 << 8)
79#define SPI_CR2_DS_9BIT (0x8 << 8)
80#define SPI_CR2_DS_10BIT (0x9 << 8)
81#define SPI_CR2_DS_11BIT (0xA << 8)
82#define SPI_CR2_DS_12BIT (0xB << 8)
83#define SPI_CR2_DS_13BIT (0xC << 8)
84#define SPI_CR2_DS_14BIT (0xD << 8)
85#define SPI_CR2_DS_15BIT (0xE << 8)
86#define SPI_CR2_DS_16BIT (0xF << 8)
87/**@}*/
88#define SPI_CR2_DS_MASK (0xF << 8)
89
90/* NSSP: NSS pulse management */
91#define SPI_CR2_NSSP (1 << 3)
92
93/* --- SPI_SR values ------------------------------------------------------- */
94
95/* FTLVL[1:0]: FIFO Transmission Level */
96#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
97#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
98#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
99#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)
100
101/* FRLVL[1:0]: FIFO Reception Level */
102#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
103#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
104#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
105#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)
106
107/* FRE : TI frame format error */
108#define SPI_SR_FRE (1 << 8)
109
110/* --- Function prototypes ------------------------------------------------- */
111
113int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
114 uint32_t lsbfirst);
115void spi_set_crcl_8bit(uint32_t spi);
116void spi_set_crcl_16bit(uint32_t spi);
117void spi_set_data_size(uint32_t spi, uint16_t data_s);
118void spi_fifo_reception_threshold_8bit(uint32_t spi);
119void spi_fifo_reception_threshold_16bit(uint32_t spi);
120void spi_i2s_mode_spi_mode(uint32_t spi);
121void spi_send8(uint32_t spi, uint8_t data);
122uint8_t spi_read8(uint32_t spi);
123
125
126/** @cond */
127#else
128#warning "spi_common_v2.h should not be included explicitly, only via spi.h"
129#endif
130/** @endcond */
131/**@}*/
132
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void spi_set_data_size(uint32_t spi, uint16_t data_s)
SPI Set data size.
void spi_i2s_mode_spi_mode(uint32_t spi)
void spi_set_crcl_16bit(uint32_t spi)
SPI Set CRC length to 16 bits.
void spi_send8(uint32_t spi, uint8_t data)
Definition: spi_common_v2.c:97
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t lsbfirst)
Configure the SPI as Master.
Definition: spi_common_v2.c:76
void spi_set_crcl_8bit(uint32_t spi)
SPI Set CRC length to 8 bits.
uint8_t spi_read8(uint32_t spi)
void spi_fifo_reception_threshold_16bit(uint32_t spi)
SPI Set reception threshold to 16 bits.
void spi_fifo_reception_threshold_8bit(uint32_t spi)
SPI Set reception threshold to 8 bits.