GD32F1X0

Here is a list of all modules:

[detail level 1234]

▼CM3 Defines	Defined Constants and Types for Cortex M3 core features
Debugging	Macros and functions to aid in debugging
▼Cortex Core Defines	libopencm3 Defined Constants and Types for the Cortex Core
Cortex Core Atomic support Defines	Atomic operation support
Cortex-M Data Watch and Trace unit.	System Control Space (SCS) => Data Watchpoint and Trace (DWT)
Cortex-M Flash Patch and Breakpoint (FPB) unit
Cortex-M Instrumentation Trace Macrocell (ITM)
▼Cortex-M MPU Defines	libopencm3 Cortex Memory Protection Unit
MPU Registers
MPU TYPE register fields	The MPU_TYPE register is always available, even if the MPU is not implemented
MPU CTRL register fields	Defines for the Control Register
MPU RNR register fields	Defines for the Region Number Register
MPU RBAR register fields	Defines for the Region Base Address Register
▼MPU RASR register fields	Defines for the Region Attribute and Size Register
MPU RASR Attributes	Not all attributes are available on v6m
▼Cortex-M NVIC Defines	libopencm3 Cortex Nested Vectored Interrupt Controller
NVIC Registers
Cortex M0/M3/M4 System Interrupts	IRQ numbers -3 and -6 to -9 are reserved
User interrupts for GD32F1x0 Series
▼Cortex-M System Control Block	The System Control Block is a section of the System Control Space
SCB Registers
SCB_CPUID Values
SCB_ICSR Values
SCB_VTOR Values
SCB_AICR Values
SCB_SCR Values
SCB_CCR Values
▼Cortex-M System Control Space	The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control
SCS Registers
▼Cortex-M SysTick Defines	libopencm3 Defined Constants and Types for the Cortex SysTick
▼STK_CSR Values
Clock source selection
STK_RVR Values
STK_CALIB Values
Cortex-M Trace Port Interface Unit (TPIU)
▼Cortex Core Peripheral APIs	APIs for Cortex Core peripherals
DWT	libopencm3 Cortex-M Data Watchpoint and Trace unit
NVIC	libopencm3 Cortex Nested Vectored Interrupt Controller
SCB	libopencm3 Cortex-M System Control Block
SysTick	libopencm3 Cortex System Tick Timer
Coresight Registers	CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals
▼Peripheral APIs	APIs for device peripherals
FLASH peripheral API	libopencm3 GD32F1x0 FLASH
RCC peripheral API	libopencm3 GD32F1x0 Reset and Clock Control
GPIO peripheral API
GD32F1x0xx	Libraries for GigaDevices GD32F1x0xx series
▼GD32F1x0xx Defines	Defined Constants and Types for the GD32F1x0xx series
▼FLASH Defines	Defined Constants and Types for the GD32F1x0 Flash memory
FLASH Wait States
▼GPIO Defines	Defined Constants and Types for the GD32F1x0 General Purpose I/O
GPIO Pin Identifiers
GPIO Port IDs
GPIO Pin Direction and Analog/Digital Mode
GPIO Output Pin Driver Type
GPIO Output Pin Speed
GPIO Output Pin Pullup
Alternate Function Pin Selection
▼RCC Defines	Defined Constants and Types for the GD32F1x0 Reset and Clock Control
USBPRE: USB prescaler (RCC_CFGR[23:22])
PLLMUL: PLL multiplication factor
PLLXTPRE: HSE divider for PLL entry
PLLSRC: PLL entry clock source
ADCPRE: ADC prescaler
RCC_CFGR APBx prescale factors	These can be used for both APB1 and APB2 prescaling
HPRE: AHB prescaler
SW: System clock switch
RCC_CFGR Deprecated dividers	Older compatible definitions to ease migration
RCC_APB2RSTR reset values values
RCC_APB1RSTR reset values values
RCC_AHBENR enable values
RCC_APB2ENR enable values
RCC_APB1ENR enable values
RCC_AHBRSTR reset values values
User interrupt service routines (ISR) prototypes for GD32F1x0 Series
User interrupt service routines (ISR) defaults for GD32F1x0 Series