libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
adc_common_v2_single.h
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1/** @addtogroup adc_defines
2
3@author @htmlonly &copy; @endhtmlonly 2015 Karl Palsson <karlp@tweak.net.au>
4
5 */
6
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
11 *
12 * This library is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU Lesser General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU Lesser General Public License for more details.
21 *
22 * You should have received a copy of the GNU Lesser General Public License
23 * along with this library. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26/**@{*/
27
28/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
29The order of header inclusion is important. adc.h includes the device
30specific memorymap.h header before including this header file.*/
31
32/*
33 * The adc v2 peripheral optionally supports per channel sampling, injected
34 * sequences, watchdogs, offsets and other "advanced" features, and is
35 * found on the (so far) F3 and L4,
36 * or only a much "simpler" version as found on (so far) f0 and l0.
37 */
38
39/** @cond */
40#ifdef LIBOPENCM3_ADC_H
41/** @endcond */
42#ifndef LIBOPENCM3_ADC_COMMON_V2_SINGLE_H
43#define LIBOPENCM3_ADC_COMMON_V2_SINGLE_H
44
45/** @addtogroup adc_registers
46 *@{*/
47/* ----- ADC registers -----------------------------------------------------*/
48/** Channel Select Register */
49#define ADC_CHSELR(adc) MMIO32((adc) + 0x28)
50/**@}*/
51
52/* ----- ADC registers values -----------------------------------------------*/
53/* ADC_CFGR1 values */
54/** @addtogroup adc_cfgr1
55@{*/
56/** Wait conversion mode */
57#define ADC_CFGR1_WAIT (1<<14)
58/** Auto off mode */
59#define ADC_CFGR1_AUTOFF (1 << 15)
60
61/** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */
62#define ADC_CFGR1_SCANDIR (1 << 2)
63/**@}*/
64
65/* ADC_CHSELR Values --------------------------------------------------------*/
66/** @defgroup adc_chselr CHSELR ADC Channel Selection register
67@{*/
68#define ADC_CHSELR_CHSEL(x) (1 << (x))
69/**@}*/
70
71/* --- Function prototypes ------------------------------------------------- */
72
74
76
77#endif
78/** @cond */
79#endif
80/** @endcond */
81/**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33