libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/f0/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
5 *
6 * .. based on file from F4.
7 *
8 * This library is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public License
19 * along with this library. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef LIBOPENCM3_MEMORYMAP_H
23#define LIBOPENCM3_MEMORYMAP_H
24
25#include <libopencm3/cm3/memorymap.h>
26
27/* --- STM32 specific peripheral definitions ------------------------------- */
28
29/* Memory map for all buses */
30#define FLASH_BASE (0x08000000U)
31#define PERIPH_BASE (0x40000000U)
32#define INFO_BASE (0x1ffff000U)
33#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000000)
34#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000)
35#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000)
36
37/* Register boundary addresses */
38
39/* APB1 */
40#define TIM2_BASE (PERIPH_BASE_APB + 0x0000)
41#define TIM3_BASE (PERIPH_BASE_APB + 0x0400)
42
43#define TIM6_BASE (PERIPH_BASE_APB + 0x1000)
44#define TIM7_BASE (PERIPH_BASE_APB + 0x1400)
45
46#define TIM14_BASE (PERIPH_BASE_APB + 0x2000)
47/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
48#define RTC_BASE (PERIPH_BASE_APB + 0x2800)
49#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00)
50#define IWDG_BASE (PERIPH_BASE_APB + 0x3000)
51/* PERIPH_BASE_APB + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
52#define SPI2_BASE (PERIPH_BASE_APB + 0x3800)
53/* PERIPH_BASE_APB + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
54#define USART2_BASE (PERIPH_BASE_APB + 0x4400)
55#define USART3_BASE (PERIPH_BASE_APB + 0x4800)
56#define USART4_BASE (PERIPH_BASE_APB + 0x4C00)
57#define USART5_BASE (PERIPH_BASE_APB + 0x5000)
58
59#define I2C1_BASE (PERIPH_BASE_APB + 0x5400)
60#define I2C2_BASE (PERIPH_BASE_APB + 0x5800)
61#define USB_DEV_FS_BASE (PERIPH_BASE_APB + 0x5C00)
62#define USB_PMA_BASE (PERIPH_BASE_APB + 0x6000)
63#define BX_CAN1_BASE (PERIPH_BASE_APB + 0x6400)
64
65#define CRS_BASE (PERIPH_BASE_APB + 0x6C00)
66#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)
67#define DAC_BASE (PERIPH_BASE_APB + 0x7400)
68#define CEC_BASE (PERIPH_BASE_APB + 0x7800)
69
70#define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000)
71#define EXTI_BASE (PERIPH_BASE_APB + 0x10400)
72
73#define USART6_BASE (PERIPH_BASE_APB + 0x11400)
74#define USART7_BASE (PERIPH_BASE_APB + 0x11800)
75#define USART8_BASE (PERIPH_BASE_APB + 0x11C00)
76
77#define ADC_BASE (PERIPH_BASE_APB + 0x12400)
78#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00)
79#define SPI1_BASE (PERIPH_BASE_APB + 0x13000)
80
81#define USART1_BASE (PERIPH_BASE_APB + 0x13800)
82#define TIM15_BASE (PERIPH_BASE_APB + 0x14000)
83#define TIM16_BASE (PERIPH_BASE_APB + 0x14400)
84#define TIM17_BASE (PERIPH_BASE_APB + 0x14800)
85
86#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)
87
88/* AHB1 */
89#define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000)
90/* DMA is the name in the F0 refman, but all other stm32's use DMA1 */
91#define DMA1_BASE DMA_BASE
92#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)
93
94#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)
95
96#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)
97
98#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
99
100#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)
101
102/* AHB2 */
103#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)
104#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)
105#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)
106#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00)
107#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)
108#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)
109
110/* Device Electronic Signature */
111#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU)
112#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU)
113#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
114#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
115#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
116
117/* ST provided factory calibration values @ 3.3V */
118#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA)
119#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8)
120#define ST_TSENSE_CAL2_110C MMIO16(0x1FFFF7C2)
121
122#endif