libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
bkp.h
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1/**
2 * @defgroup bkp_defines BKP Defines
3 * @ingroup STM32F1xx_defines
4 * @brief <b>Defined Constants and Types for the Backup Registers</b>
5 *
6 * This file is part of the libopencm3 project.
7 *
8 * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
9 *
10 * This library is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU Lesser General Public License as published by
12 * the Free Software Foundation, either version 3 of the License, or
13 * (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public License
21 * along with this library. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24#ifndef LIBOPENCM3_BKP_H
25#define LIBOPENCM3_BKP_H
26
27/** @defgroup BKP_registers BKP Registers
28 * @ingroup bkp_defines
29@{*/
30/* Backup data register 1 (BKP_DR1) */
31#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04)
32
33/* Backup data register 2 (BKP_DR2) */
34#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08)
35
36/* Backup data register 3 (BKP_DR3) */
37#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C)
38
39/* Backup data register 4 (BKP_DR4) */
40#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10)
41
42/* Backup data register 5 (BKP_DR5) */
43#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14)
44
45/* Backup data register 6 (BKP_DR6) */
46#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18)
47
48/* Backup data register 7 (BKP_DR7) */
49#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C)
50
51/* Backup data register 8 (BKP_DR8) */
52#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20)
53
54/* Backup data register 9 (BKP_DR9) */
55#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24)
56
57/* Backup data register 10 (BKP_DR10) */
58#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28)
59
60/** RTC clock calibration register (BKP_RTCCR) */
61#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C)
62
63/** Backup control register (BKP_CR) */
64#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30)
65
66/** Backup control/status register (BKP_CSR) */
67#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34)
68
69/* Backup data register 11 (BKP_DR11) */
70#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40)
71
72/* Backup data register 12 (BKP_DR12) */
73#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44)
74
75/* Backup data register 13 (BKP_DR13) */
76#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48)
77
78/* Backup data register 14 (BKP_DR14) */
79#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C)
80
81/* Backup data register 15 (BKP_DR15) */
82#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50)
83
84/* Backup data register 16 (BKP_DR16) */
85#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54)
86
87/* Backup data register 17 (BKP_DR17) */
88#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58)
89
90/* Backup data register 18 (BKP_DR18) */
91#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C)
92
93/* Backup data register 19 (BKP_DR19) */
94#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60)
95
96/* Backup data register 20 (BKP_DR20) */
97#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64)
98
99/* Backup data register 21 (BKP_DR21) */
100#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68)
101
102/* Backup data register 22 (BKP_DR22) */
103#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C)
104
105/* Backup data register 23 (BKP_DR23) */
106#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70)
107
108/* Backup data register 24 (BKP_DR24) */
109#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74)
110
111/* Backup data register 25 (BKP_DR25) */
112#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78)
113
114/* Backup data register 26 (BKP_DR26) */
115#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C)
116
117/* Backup data register 27 (BKP_DR27) */
118#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80)
119
120/* Backup data register 28 (BKP_DR28) */
121#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84)
122
123/* Backup data register 29 (BKP_DR29) */
124#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88)
125
126/* Backup data register 30 (BKP_DR30) */
127#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C)
128
129/* Backup data register 31 (BKP_DR31) */
130#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90)
131
132/* Backup data register 32 (BKP_DR32) */
133#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94)
134
135/* Backup data register 33 (BKP_DR33) */
136#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98)
137
138/* Backup data register 34 (BKP_DR34) */
139#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C)
140
141/* Backup data register 35 (BKP_DR35) */
142#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0)
143
144/* Backup data register 36 (BKP_DR36) */
145#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4)
146
147/* Backup data register 37 (BKP_DR37) */
148#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8)
149
150/* Backup data register 38 (BKP_DR38) */
151#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC)
152
153/* Backup data register 39 (BKP_DR39) */
154#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0)
155
156/* Backup data register 40 (BKP_DR40) */
157#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4)
158
159/* Backup data register 41 (BKP_DR41) */
160#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8)
161
162/* Backup data register 42 (BKP_DR42) */
163#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC)
164/**@}*/
165
166/** @defgroup BKP_RTCCR_Values BKP_RTCCR Values
167 * @ingroup bkp_defines
168@{*/
169/** ASOS: Alarm or second output selection */
170#define BKP_RTCCR_ASOS (1 << 9)
171
172/** ASOE: Alarm or second output enable */
173#define BKP_RTCCR_ASOE (1 << 8)
174
175/** CCO: Calibration clock output */
176#define BKP_RTCCR_CCO (1 << 7)
177
178/** CAL[6:0]: Calibration value */
179#define BKP_RTCCR_CAL_LSB 0
180/**@}*/
181
182/** @defgroup BKP_CR_Values BKP_CR Values
183 * @ingroup bkp_defines
184@{*/
185/** TPAL: TAMPER pin active level */
186#define BKP_CR_TPAL (1 << 1)
187
188/** TPE: TAMPER pin enable */
189#define BKP_CR_TPE (1 << 0)
190/**@}*/
191
192/** @defgroup BKP_CSR_Values BKP_CSR Values
193 * @ingroup bkp_defines
194@{*/
195/** TIF: Tamper interrupt flag */
196#define BKP_CSR_TIF (1 << 9)
197
198/** TEF: Tamper event flag */
199#define BKP_CSR_TEF (1 << 8)
200
201/** TPIE: TAMPER pin interrupt enable */
202#define BKP_CSR_TPIE (1 << 2)
203
204/** CTI: Clear tamper interrupt */
205#define BKP_CSR_CTI (1 << 1)
206
207/** CTE: Clear tamper event */
208#define BKP_CSR_CTE (1 << 0)
209/**@}*/
210
211#endif