libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
f4/adc.h
Go to the documentation of this file.
1 /** @defgroup adc_defines ADC Defines
2 
3 @brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital
4 Converters</b>
5 
6 @ingroup STM32F4xx_defines
7 
8 @version 1.0.0
9 
10 @author @htmlonly &copy; @endhtmlonly 2019
11 Matthew Lai <m@matthewlai.ca>
12 @author @htmlonly &copy; @endhtmlonly 2009
13 Edward Cheeseman <evbuilder@users.sourceforge.net>
14 
15 @date 31 August 2012
16 
17 LGPL License Terms @ref lgpl_license
18  */
19 /*
20  * This file is part of the libopencm3 project.
21  *
22  * Copyright (C) 2019 Matthew Lai <m@matthewlai.ca>
23  * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
24  *
25  * This library is free software: you can redistribute it and/or modify
26  * it under the terms of the GNU Lesser General Public License as published by
27  * the Free Software Foundation, either version 3 of the License, or
28  * (at your option) any later version.
29  *
30  * This library is distributed in the hope that it will be useful,
31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33  * GNU Lesser General Public License for more details.
34  *
35  * You should have received a copy of the GNU Lesser General Public License
36  * along with this library. If not, see <http://www.gnu.org/licenses/>.
37  */
38 
39 #ifndef LIBOPENCM3_ADC_H
40 #define LIBOPENCM3_ADC_H
41 
43 
44 /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
45 #define ADC_JOFR1(block) MMIO32((block) + 0x14)
46 #define ADC_JOFR2(block) MMIO32((block) + 0x18)
47 #define ADC_JOFR3(block) MMIO32((block) + 0x1c)
48 #define ADC_JOFR4(block) MMIO32((block) + 0x20)
49 
50 /* ADC watchdog high threshold register (ADC_HTR) */
51 #define ADC_HTR(block) MMIO32((block) + 0x24)
52 
53 /* ADC watchdog low threshold register (ADC_LTR) */
54 #define ADC_LTR(block) MMIO32((block) + 0x28)
55 
56 /* ADC regular sequence register 1 (ADC_SQR1) */
57 #define ADC_SQR1(block) MMIO32((block) + 0x2c)
58 
59 /* ADC regular sequence register 2 (ADC_SQR2) */
60 #define ADC_SQR2(block) MMIO32((block) + 0x30)
61 
62 /* ADC regular sequence register 3 (ADC_SQR3) */
63 #define ADC_SQR3(block) MMIO32((block) + 0x34)
64 
65 /* ADC injected sequence register (ADC_JSQR) */
66 #define ADC_JSQR(block) MMIO32((block) + 0x38)
67 
68 /* ADC injected data register x (ADC_JDRx) (x=1..4) */
69 #define ADC_JDR1(block) MMIO32((block) + 0x3c)
70 #define ADC_JDR2(block) MMIO32((block) + 0x40)
71 #define ADC_JDR3(block) MMIO32((block) + 0x44)
72 #define ADC_JDR4(block) MMIO32((block) + 0x48)
73 
74 /* ADC regular data register (ADC_DR) */
75 #define ADC_DR(block) MMIO32((block) + 0x4c)
76 
77 /** @defgroup adc_channel ADC Channel Numbers
78  * @ingroup adc_defines
79  * Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18!
80  *@{*/
81 #define ADC_CHANNEL_TEMP_F40 16
82 #define ADC_CHANNEL_TEMP_F42 18
83 #define ADC_CHANNEL_VREF 17
84 #define ADC_CHANNEL_VBAT 18
85 /**@}*/
86 
87 
88 /* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
89 #define ADC_CR1_AWDCH_MAX 18
90 
91 
92 /* --- Convenience macros -------------------------------------------------- */
93 /* EXTSEL[3:0]: External event selection for regular group. */
94 /****************************************************************************/
95 /** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
96 @ingroup adc_defines
97 
98 @{*/
99 /** Timer 1 Compare Output 1 */
100 #define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
101 /** Timer 1 Compare Output 2 */
102 #define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
103 /** Timer 1 Compare Output 3 */
104 #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
105 /** Timer 2 Compare Output 2 */
106 #define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
107 /** Timer 2 Compare Output 3 */
108 #define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24)
109 /** Timer 2 Compare Output 4 */
110 #define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24)
111 /** Timer 2 TRGO Event */
112 #define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24)
113 /** Timer 3 Compare Output 1 */
114 #define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24)
115 /** Timer 3 TRGO Event */
116 #define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24)
117 /** Timer 4 Compare Output 4 */
118 #define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24)
119 /** Timer 5 Compare Output 1 */
120 #define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24)
121 /** Timer 5 Compare Output 2 */
122 #define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24)
123 /** Timer 5 Compare Output 3 */
124 #define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24)
125 /** Timer 8 Compare Output 1 */
126 #define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24)
127 /** Timer 8 TRGO Event */
128 #define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24)
129 /** EXTI Line 11 Event */
130 #define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24)
131 /**@}*/
132 
133 /* JEXTSEL[3:0]: External event selection for injected group. */
134 /****************************************************************************/
135 /** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group
136 @ingroup adc_defines
137 
138 @{*/
139 #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16)
140 #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16)
141 #define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16)
142 #define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16)
143 #define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16)
144 #define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16)
145 #define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16)
146 #define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16)
147 #define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16)
148 #define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16)
149 #define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16)
150 #define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16)
151 #define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16)
152 #define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16)
153 #define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16)
154 #define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16)
155 /**@}*/
156 
157 /* ADC_SMPRG ADC Sample Time Selection for Channels */
158 /** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
159 @ingroup adc_defines
160 
161 @{*/
162 #define ADC_SMPR_SMP_3CYC 0x0
163 #define ADC_SMPR_SMP_15CYC 0x1
164 #define ADC_SMPR_SMP_28CYC 0x2
165 #define ADC_SMPR_SMP_56CYC 0x3
166 #define ADC_SMPR_SMP_84CYC 0x4
167 #define ADC_SMPR_SMP_112CYC 0x5
168 #define ADC_SMPR_SMP_144CYC 0x6
169 #define ADC_SMPR_SMP_480CYC 0x7
170 /**@}*/
171 
172 /* --- ADC_SQR1 values ----------------------------------------------------- */
173 #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
174 
175 #define ADC_SQR_MAX_CHANNELS_REGULAR 16
176 
177 /* ADCPRE: ADC prescaler. */
178 /****************************************************************************/
179 /** @defgroup adc_ccr_adcpre ADC Prescale
180 @ingroup adc_defines
181 
182 @{*/
183 #define ADC_CCR_ADCPRE_BY2 (0x0 << 16)
184 #define ADC_CCR_ADCPRE_BY4 (0x1 << 16)
185 #define ADC_CCR_ADCPRE_BY6 (0x2 << 16)
186 #define ADC_CCR_ADCPRE_BY8 (0x3 << 16)
187 /**@}*/
188 #define ADC_CCR_ADCPRE_MASK (0x3 << 16)
189 #define ADC_CCR_ADCPRE_SHIFT 16
190 
191 
193 
194 void adc_set_multi_mode(uint32_t mode);
195 void adc_enable_vbat_sensor(void);
196 void adc_disable_vbat_sensor(void);
197 
198 END_DECLS
199 
200 #endif
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void adc_disable_vbat_sensor(void)
Disable The VBat Sensor.
void adc_set_multi_mode(uint32_t mode)
ADC Set Dual/Triple Mode.
void adc_enable_vbat_sensor(void)
Enable The VBat Sensor.