libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/f4/memorymap.h
Go to the documentation of this file.
1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_MEMORYMAP_H
21#define LIBOPENCM3_MEMORYMAP_H
22
24
25/* --- STM32F4 specific peripheral definitions ----------------------------- */
26
27/* Memory map for all busses */
28#define FLASH_BASE (0x08000000U)
29#define PERIPH_BASE (0x40000000U)
30#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
31#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
32#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
33#define PERIPH_BASE_AHB2 0x50000000U
34#define PERIPH_BASE_AHB3 0x60000000U
35
36/* Register boundary addresses */
37
38/* APB1 */
39#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
40#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
41#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
42#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
43#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
44#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
45#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
46#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
47#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
48#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)
49#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
50#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
51#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
52#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)
53#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
54#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
55#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)
56#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
57#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
58#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
59#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
60#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
61#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
62#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
63#define FMPI2C1_BASE (PERIPH_BASE_APB1 + 0x6000)
64#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
65#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
66/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
67#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
68#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
69#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800)
70#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)
71/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */
72
73/* APB2 */
74#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
75#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
76/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
77#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
78#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
79/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
80#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
81#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100)
82#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)
83#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)
84/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
85#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)
86/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
87#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
88#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)
89/* PERIPH_BASE_APB2 + 0x3500 (0x4001 3500 - 0x4001 37FF): Reserved */
90#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
91#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
92#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
93#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
94#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
95/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */
96#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)
97#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)
98#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)
99#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800)
100#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)
101/* PERIPH_BASE_APB2 + 0x7400 (0x4001 7400 - 0x4001 FFFF): Reserved */
102
103/* AHB1 */
104#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
105#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
106#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
107#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
108#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
109#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
110#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
111#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
112#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
113#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)
114#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)
115/* PERIPH_BASE_AHB1 + 0x2C00 (0x4002 2C00 - 0x4002 2FFF): Reserved */
116#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
117/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
118#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
119#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
120#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
121/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
122#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
123#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
124/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
125#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
126#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U)
127/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */
128#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
129/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
130
131/* AHB2 */
132#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)
133/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
134#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
135/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
136#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
137#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
138/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */
139#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
140/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
141
142/* AHB3 */
143/* Address: 0x60000000 */
144#define FMC_BANK1 (PERIPH_BASE_AHB3)
145/* Address: 0x70000000 */
146#define FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U)
147/* Address: 0x80000000 */
148#define FMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U)
149/* Address: 0x90000000 */
150#define QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U)
151#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
152#define FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
153#define QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)
154/* Address: 0xC0000000 */
155#define FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U)
156/* Address: 0xD0000000 */
157#define FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U)
158
159/* PPIB */
160#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
161
162/* Device Electronic Signature */
163#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U)
164#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U)
165#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
166#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
167#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
168
169/* ST provided factory calibration values @ 3.3V */
170#define ST_VREFINT_CAL MMIO16(0x1FFF7A2A)
171#define ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C)
172#define ST_TSENSE_CAL2_110C MMIO16(0x1FFF7A2E)
173
174#endif