libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
adc_common_v2_multi.h
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1/** @addtogroup adc_defines
2
3@author @htmlonly &copy; @endhtmlonly 2015 Karl Palsson <karlp@tweak.net.au>
4
5 */
6
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
11 *
12 * This library is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU Lesser General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU Lesser General Public License for more details.
21 *
22 * You should have received a copy of the GNU Lesser General Public License
23 * along with this library. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26/**@{*/
27
28/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
29The order of header inclusion is important. adc.h includes the device
30specific memorymap.h header before including this header file.*/
31
32/** @cond */
33#ifdef LIBOPENCM3_ADC_H
34/** @endcond */
35#ifndef LIBOPENCM3_ADC_COMMON_V2_MULTI_H
36#define LIBOPENCM3_ADC_COMMON_V2_MULTI_H
37
38/*
39 * The adc v2 peripheral optionally supports per channel sampling, injected
40 * sequences, watchdogs, offsets and other "advanced" features, and is
41 * found on the (so far) F3 and L4,
42 * or only a much "simpler" version as found on (so far) f0 and l0.
43 */
44
45/** @addtogroup adc_registers
46 *@{*/
47/* ----- ADC registers -----------------------------------------------------*/
48/* Sample Time Register 2 */
49#define ADC_SMPR2(adc) MMIO32((adc) + 0x18)
50/* Watchdog Threshold Register 2 */
51#define ADC_TR2(adc) MMIO32((adc) + 0x24)
52/* Watchdog Threshold Register 3 */
53#define ADC_TR3(adc) MMIO32((adc) + 0x28)
54/* Regular Sequence Register x (ADCx_SQRy, x=1..4, y=1..4) SQRy */
55#define ADC_SQR1(adc) MMIO32((adc) + 0x30)
56#define ADC_SQR2(adc) MMIO32((adc) + 0x34)
57#define ADC_SQR3(adc) MMIO32((adc) + 0x38)
58#define ADC_SQR4(adc) MMIO32((adc) + 0x3C)
59
60/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */
61#define ADC_JSQR(adc) MMIO32((adc) + 0x4c)
62
63/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */
64#define ADC_OFR1(adc) MMIO32((adc) + 0x60)
65#define ADC_OFR2(adc) MMIO32((adc) + 0x64)
66#define ADC_OFR3(adc) MMIO32((adc) + 0x68)
67#define ADC_OFR4(adc) MMIO32((adc) + 0x6C)
68
69/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */
70#define ADC_JDR1(adc) MMIO32((adc) + 0x80)
71#define ADC_JDR2(adc) MMIO32((adc) + 0x84)
72#define ADC_JDR3(adc) MMIO32((adc) + 0x88)
73#define ADC_JDR4(adc) MMIO32((adc) + 0x8C)
74
75/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */
76#define ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)
77/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */
78#define ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)
79
80/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */
81#define ADC_DIFSEL(adc) MMIO32((adc) + 0xB0)
82
83/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */
84#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4)
85
86/* ADC common (shared) registers */
87#define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0)
88#define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xc)
89/**@}*/
90
91/* --- Register values ------------------------------------------------------*/
92/* ADC_ISR Values -----------------------------------------------------------*/
93
94/* QOVF: Injected context queue overflow */
95#define ADC_ISR_JQOVF (1 << 10)
96/* AWD3: Analog watchdog 3 flag */
97#define ADC_ISR_AWD3 (1 << 9)
98/* AWD2: Analog watchdog 2 flag */
99#define ADC_ISR_AWD2 (1 << 8)
100/* JEOS: Injected channel end of sequence flag */
101#define ADC_ISR_JEOS (1 << 6)
102/* JEOC: Injected channel end of conversion flag */
103#define ADC_ISR_JEOC (1 << 5)
104
105/* ADC_IER Values -----------------------------------------------------------*/
106
107/* JQOVFIE: Injected context queue overflow interrupt enable */
108#define ADC_IER_JQOVFIE (1 << 10)
109/* AWD3IE: Analog watchdog 3 interrupt enable */
110#define ADC_IER_AWD3IE (1 << 9)
111/* AWD2IE: Analog watchdog 2 interrupt enable */
112#define ADC_IER_AWD2IE (1 << 8)
113/* JEOSIE: End of injected sequence of conversions interrupt enable */
114#define ADC_IER_JEOSIE (1 << 6)
115/* JEOCIE: End of injected conversion interrupt enable */
116#define ADC_IER_JEOCIE (1 << 5)
117
118/* ADC_CR Values ------------------------------------------------------------*/
119
120/* ADCALDIF: Differential mode for calibration */
121#define ADC_CR_ADCALDIF (1 << 30)
122/* JADSTP: ADC stop of injected conversion command */
123#define ADC_CR_JADSTP (1 << 5)
124/* JADSTART: ADC start of injected conversion */
125#define ADC_CR_JADSTART (1 << 3)
126
127/* ADC_CFGR1 Values ---------------------------------------------------------*/
128
129/* JAUTO: Autoamtic injected group conversion */
130#define ADC_CFGR1_JAUTO (1 << 25)
131
132/* JAWD1EN: Analog watchdog 1 enable on injected channels */
133#define ADC_CFGR1_JAWD1EN (1 << 24)
134
135/* JQM: JSQR queue mode */
136#define ADC_CFGR1_JQM (1 << 21)
137
138/* JDISCEN: Discontinuous mode on injected channels */
139#define ADC_CFGR1_JDISCEN (1 << 20)
140
141/* DISCNUM[2:0]: Discontinuous mode channel count */
142#define ADC_CFGR1_DISCNUM_SHIFT 17
143#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT)
144#define ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)
145
146/* ADC_SQRx Values: Regular Sequence ordering------------------------------- */
147
148#define ADC_SQR1_L_SHIFT 0
149#define ADC_SQR1_L_MASK 0xf
150#define ADC_SQRx_SQx_MASK 0x1f
151#define ADC_SQR1_SQ1_SHIFT 6
152#define ADC_SQR1_SQ2_SHIFT 12
153#define ADC_SQR1_SQ3_SHIFT 18
154#define ADC_SQR1_SQ4_SHIFT 24
155#define ADC_SQR2_SQ5_SHIFT 0
156#define ADC_SQR2_SQ6_SHIFT 6
157#define ADC_SQR2_SQ7_SHIFT 12
158#define ADC_SQR2_SQ8_SHIFT 18
159#define ADC_SQR2_SQ9_SHIFT 24
160#define ADC_SQR3_SQ10_SHIFT 0
161#define ADC_SQR3_SQ11_SHIFT 6
162#define ADC_SQR3_SQ12_SHIFT 12
163#define ADC_SQR3_SQ13_SHIFT 18
164#define ADC_SQR3_SQ14_SHIFT 24
165#define ADC_SQR4_SQ15_SHIFT 0
166#define ADC_SQR4_SQ16_SHIFT 6
167
168/* --- Function prototypes ------------------------------------------------- */
169
170BEGIN_DECLS
171
172void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
173void adc_enable_regulator(uint32_t adc);
174void adc_disable_regulator(uint32_t adc);
175
176END_DECLS
177
178#endif
179/** @cond */
180#endif
181/** @endcond */
182/**@}*/
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
adc_set_sample_time
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
ADC Set the Sample Time for a Single Channel.
Definition: adc_common_v2_multi.c:47
adc_disable_regulator
void adc_disable_regulator(uint32_t adc)
Disable the ADC Voltage regulator You can disable the adc vreg when not in use to save power.
Definition: adc.c:50
adc_enable_regulator
void adc_enable_regulator(uint32_t adc)
Enable the ADC Voltage regulator Before any use of the ADC, the ADC Voltage regulator must be enabled...
Definition: adc.c:39