libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
crs_common_all.h
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1/** @addtogroup crs_defines
2 *
3 * @date 5 Feb 2014
4 *
5 * LGPL License Terms @ref lgpl_license
6 */
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2014 Frantisek Burian <BuFran@seznam.cz>
11 *
12 * This library is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU Lesser General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU Lesser General Public License for more details.
21 *
22 * You should have received a copy of the GNU Lesser General Public License
23 * along with this library. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26#ifndef LIBOPENCM3_CRS_H
27#define LIBOPENCM3_CRS_H
28/**@{*/
29
30/*****************************************************************************/
31/* Module definitions */
32/*****************************************************************************/
33
34#define CRS CRS_BASE
35
36/*****************************************************************************/
37/* Register definitions */
38/*****************************************************************************/
39
40#define CRS_CR MMIO32(CRS_BASE + 0x00)
41#define CRS_CFGR MMIO32(CRS_BASE + 0x04)
42#define CRS_ISR MMIO32(CRS_BASE + 0x08)
43#define CRS_ICR MMIO32(CRS_BASE + 0x0c)
44
45/*****************************************************************************/
46/* Register values */
47/*****************************************************************************/
48
49/* CEC_CR Values ------------------------------------------------------------*/
50
51#define CRS_CR_TRIM_SHIFT 8
52#define CRS_CR_TRIM (0x3F << CRS_CR_TRIM_SHIFT)
53
54#define CRS_CR_SWSYNC (1 << 7)
55#define CRS_CR_AUTOTRIMEN (1 << 6)
56#define CRS_CR_CEN (1 << 5)
57#define CRS_CR_ESYNCIE (1 << 3)
58#define CRS_CR_ERRIE (1 << 2)
59#define CRS_CR_SYNCWARNIE (1 << 1)
60#define CRS_CR_SYNCOKIE (1 << 0)
61
62/* CEC_CFGR Values ----------------------------------------------------------*/
63
64#define CRS_CFGR_SYNCPOL (1 << 31)
65
66#define CRS_CFGR_SYNCSRC_SHIFT 28
67#define CRS_CFGR_SYNCSRC (3 << CRS_CFGR_SYNCSRC_SHIFT)
68#define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT)
69#define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT)
70#define CRS_CFGR_SYNCSRC_USB_SOF (2 << CRS_CFGR_SYNCSRC_SHIFT)
71
72#define CRS_CFGR_SYNCDIV_SHIFT 24
73#define CRS_CFGR_SYNCDIV (7 << CRS_CFGR_SYNCDIV_SHIFT)
74#define CRS_CFGR_SYNCDIV_NODIV (0 << CRS_CFGR_SYNCDIV_SHIFT)
75#define CRS_CFGR_SYNCDIV_DIV2 (1 << CRS_CFGR_SYNCDIV_SHIFT)
76#define CRS_CFGR_SYNCDIV_DIV4 (2 << CRS_CFGR_SYNCDIV_SHIFT)
77#define CRS_CFGR_SYNCDIV_DIV8 (3 << CRS_CFGR_SYNCDIV_SHIFT)
78#define CRS_CFGR_SYNCDIV_DIV16 (4 << CRS_CFGR_SYNCDIV_SHIFT)
79#define CRS_CFGR_SYNCDIV_DIV32 (5 << CRS_CFGR_SYNCDIV_SHIFT)
80#define CRS_CFGR_SYNCDIV_DIV64 (6 << CRS_CFGR_SYNCDIV_SHIFT)
81#define CRS_CFGR_SYNCDIV_DIV128 (7 << CRS_CFGR_SYNCDIV_SHIFT)
82
83#define CRS_CFGR_FELIM_SHIFT 16
84#define CRS_CFGR_FELIM (0xFF << CRS_CFGR_FELIM_SHIFT)
85#define CRS_CFGR_FELIM_VAL(x) ((x) << CRS_CFGR_FELIM_SHIFT)
86
87#define CRS_CFGR_RELOAD_SHIFT 0
88#define CRS_CFGR_RELOAD (0xFFFF << CRS_CFGR_RELOAD_SHIFT)
89#define CRS_CFGR_RELOAD_VAL(x) ((x) << CRS_CFGR_RELOAD_SHIFT)
90
91/* CEC_ISR Values -----------------------------------------------------------*/
92
93#define CRS_ISR_FECAP_SHIFT 16
94#define CRS_ISR_FECAP (0xFFFF << CRS_ISR_FECAP_SHIFT)
95
96#define CRS_ISR_FEDIR (1 << 15)
97#define CRS_ISR_TRIMOVF (1 << 10)
98#define CRS_ISR_SYNCMISS (1 << 9)
99#define CRS_ISR_SYNCERR (1 << 8)
100#define CRS_ISR_ESYNCF (1 << 3)
101#define CRS_ISR_ERRF (1 << 2)
102#define CRS_ISR_SYNCWARNF (1 << 1)
103#define CRS_ISR_SYNCOOKF (1 << 0)
104
105/* CEC_ICR Values -----------------------------------------------------------*/
106
107#define CRS_ICR_ESYNCC (1 << 3)
108#define CRS_ICR_ERRC (1 << 2)
109#define CRS_ICR_SYNCWARNC (1 << 1)
110#define CRS_ICR_SYNCOKC (1 << 0)
111
112/*****************************************************************************/
113/* API definitions */
114/*****************************************************************************/
115
116/*****************************************************************************/
117/* API Functions */
118/*****************************************************************************/
119
121
122void crs_autotrim_usb_enable(void);
123
125/**@}*/
126
127#endif
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void crs_autotrim_usb_enable(void)
This function enables automatic trimming of internal RC oscillator by USB SOF frames.