SWM050

Here is a list of all modules:

[detail level 123456]

▼CM3 Defines	Defined Constants and Types for Cortex M3 core features
Debugging	Macros and functions to aid in debugging
▼Cortex Core Defines	libopencm3 Defined Constants and Types for the Cortex Core
Cortex Core Atomic support Defines	Atomic operation support
Cortex-M Data Watch and Trace unit.	System Control Space (SCS) => Data Watchpoint and Trace (DWT)
Cortex-M Flash Patch and Breakpoint (FPB) unit
Cortex-M Instrumentation Trace Macrocell (ITM)
▼Cortex-M MPU Defines	libopencm3 Cortex Memory Protection Unit
MPU Registers
MPU TYPE register fields	The MPU_TYPE register is always available, even if the MPU is not implemented
MPU CTRL register fields	Defines for the Control Register
MPU RNR register fields	Defines for the Region Number Register
MPU RBAR register fields	Defines for the Region Base Address Register
▼MPU RASR register fields	Defines for the Region Attribute and Size Register
MPU RASR Attributes	Not all attributes are available on v6m
▼Cortex-M NVIC Defines	libopencm3 Cortex Nested Vectored Interrupt Controller
NVIC Registers
Cortex M0/M3/M4 System Interrupts	IRQ numbers -3 and -6 to -9 are reserved
User interrupts for SWM050 series
▼Cortex-M System Control Block	The System Control Block is a section of the System Control Space
SCB Registers
SCB_CPUID Values
SCB_ICSR Values
SCB_VTOR Values
SCB_AICR Values
SCB_SCR Values
SCB_CCR Values
▼Cortex-M System Control Space	The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control
SCS Registers
▼Cortex-M SysTick Defines	libopencm3 Defined Constants and Types for the Cortex SysTick
▼STK_CSR Values
Clock source selection
STK_RVR Values
STK_CALIB Values
Cortex-M Trace Port Interface Unit (TPIU)
▼Cortex Core Peripheral APIs	APIs for Cortex Core peripherals
DWT	libopencm3 Cortex-M Data Watchpoint and Trace unit
NVIC	libopencm3 Cortex Nested Vectored Interrupt Controller
SCB	libopencm3 Cortex-M System Control Block
SysTick	libopencm3 Cortex System Tick Timer
Coresight Registers	CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals
▼Peripheral APIs	APIs for device peripherals
Clock peripheral API	SWM050 Clock API
Flash peripheral API	SWM050 Flash API
GPIO peripheral API	SWM050 GPIO API
Power/Sleep API	SWM050 Power API
SYSCON peripheral API	SWM050 SYSCON API
Timer peripheral API	SWM050 Timer API
Watchdog peripheral API	SWM050 WDT API
SWM050	Libraries for Synwit SWM050 series
▼SWM050 Defines	Defined Constants and Types for the SWM050 series
▼Clock Defines	Defined Constants and Types for the SWM050 System Clock
▼Base Clock Speeds
Mask used to set the clock divider
Flash Defines	Defined Constants and Types for the SWM050 Flash API
▼GPIO Defines	Defined Constants and Types for the SWM050 General Purpose I/O
GPIO Pin Identifiers
GPIO Pin Direction
▼GPIO Polarity
▼GPIO Interrupt Trigger Type
▼GPIO Interrupt Mask
GPIO Registers
▼Memory Map	Defined Constants for the SWM050 Memory Map
Memory Map for All Buses
Power/Sleep Defines	Defined Constants and Types for the SWM050 Power/Sleep API
▼SYSCON Defines	Defined Constants and Types for the SWM050 SYSCON peripheral
SYSCON Registers
▼SYSCTL Defines	Defined Constants and Types for the SWM050 SYSCTL Registers
SYSCTL register bit definitions
SYSCTL Registers
▼Timer Defines	Defined Constants and Types for the SWM050 Timer
▼Timer Select
▼Timer Registers
Timer Register Values
▼Watchdog Defines	Defined Constants and Types for the SWM050 Watchdog
Watchdog mode
Watchdog Registers
User interrupt service routines (ISR) prototypes for SWM050 series
User interrupt service routines (ISR) defaults for SWM050 series