54#define _CMU_REG(i) MMIO32(CMU_BASE + ((i) >> 5))
55#define _CMU_BIT(i) (1 << ((i) & 0x1f))
#define CMU_OSCENCMD_LFXOEN
#define CMU_OSCENCMD_LFRCOEN
#define CMU_OSCENCMD_HFXOEN
#define CMU_STATUS_HFRCOSEL
#define CMU_STATUS_HFXORDY
#define CMU_CMD_HFCLKSEL_HFXO
#define CMU_STATUS_LFRCORDY
#define CMU_OSCENCMD_LFRCODIS
#define CMU_STATUS_AUXHFRCORDY
#define CMU_LOCK_LOCKKEY_UNLOCK
#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV
#define CMU_CTRL_HFXOBUFCUR_MASK
#define CMU_CTRL_HFCLKDIV_NODIV
#define CMU_CTRL_HFCLKDIV_MASK
#define CMU_OSCENCMD_AUXHFRCOEN
#define CMU_OSCENCMD_HFXODIS
#define CMU_HFCORECLKDIV_HFCORECLKLEDIV
#define CMU_STATUS_LFRCOSEL
#define CMU_STATUS_HFXOSEL
#define CMU_OSCENCMD_HFRCOEN
#define CMU_STATUS_LFXORDY
#define CMU_CMD_HFCLKSEL_LFXO
#define CMU_LOCK_LOCKKEY_MASK
#define CMU_LOCK_LOCKKEY_LOCK
#define CMU_STATUS_LFXOSEL
#define CMU_CMD_HFCLKSEL_HFRCO
#define CMU_OSCENCMD_LFXODIS
#define CMU_STATUS_HFRCORDY
#define CMU_CMD_HFCLKSEL_LFRCO
#define CMU_OSCENCMD_HFRCODIS
#define CMU_OSCENCMD_AUXHFRCODIS
#define CMU_LOCK_LOCKKEY_LOCKED
#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ
@ AUXHFRCO
Internal, 1-28Mhz.
@ HFRCO
Internal, 1 - 28Mhz.
@ LFRCO
Internal, 32.768kHz.
@ LFXO
External, 32.768kHz.
void cmu_osc_off(enum cmu_osc osc)
Turn off Oscillator.
enum cmu_osc cmu_get_hfclk_source(void)
void cmu_periph_clock_enable(enum cmu_periph_clken clken)
Enable Peripheral Clock in running mode.
void cmu_periph_clock_disable(enum cmu_periph_clken clken)
Disable Peripheral Clock in running mode.
bool cmu_get_lock_flag(void)
Get CMU register lock flag.
void cmu_clock_setup_in_hfxo_out_48mhz(void)
HFXO output 48Mhz and core running at 48Mhz.
bool cmu_osc_ready_flag(enum cmu_osc osc)
Get Oscillator read flag.
void cmu_enable_lock(void)
Enable CMU registers lock.
void cmu_disable_lock(void)
Disable CMU registers lock.
void cmu_osc_on(enum cmu_osc osc)
Turn on Oscillator.
void cmu_set_hfclk_source(enum cmu_osc osc)
Set HFCLK clock source.
void cmu_wait_for_osc_ready(enum cmu_osc osc)
Wait till oscillator is not ready.
#define MSC_READCTRL_MODE_WS2