libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
timer_common.h
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1/** @addtogroup timer_defines
2 */
3/*
4 * This file is part of the libopencm3 project.
5 *
6 * Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
7 *
8 * This library is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public License
19 * along with this library. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#pragma once
23
26
27/**@{*/
28
29#define TIMER_CTRL(base) MMIO32((base) + 0x000)
30#define TIMER_CMD(base) MMIO32((base) + 0x004)
31#define TIMER_STATUS(base) MMIO32((base) + 0x008)
32#define TIMER_IEN(base) MMIO32((base) + 0x00C)
33#define TIMER_IF(base) MMIO32((base) + 0x010)
34#define TIMER_IFS(base) MMIO32((base) + 0x014)
35#define TIMER_IFC(base) MMIO32((base) + 0x018)
36#define TIMER_TOP(base) MMIO32((base) + 0x01C)
37#define TIMER_TOPB(base) MMIO32((base) + 0x020)
38#define TIMER_CNT(base) MMIO32((base) + 0x024)
39#define TIMER_ROUTE(base) MMIO32((base) + 0x028)
40
41#define TIMER_CCx_CTRL(base, x) MMIO32((base) + 0x030 + (0x10 * (x)))
42#define TIMER_CCx_CCV(base, x) MMIO32((base) + 0x034 + (0x10 * (x)))
43#define TIMER_CCx_CCVP(base, x) MMIO32((base) + 0x038 + (0x10 * (x)))
44#define TIMER_CCx_CCVB(base, x) MMIO32((base) + 0x03C + (0x10 * (x)))
45
46#define TIMER_CC0_CTRL(base) TIMER_CCx_CTRL(base, 0)
47#define TIMER_CC0_CCV(base) TIMER_CCx_CCV(base, 0)
48#define TIMER_CC0_CCVP(base) TIMER_CCx_CCVP(base, 0)
49#define TIMER_CC0_CCVB(base) TIMER_CCx_CCVB(base, 0)
50
51#define TIMER_CC1_CTRL(base) TIMER_CCx_CTRL(base, 1)
52#define TIMER_CC1_CCV(base) TIMER_CCx_CCV(base, 1)
53#define TIMER_CC1_CCVP(base) TIMER_CCx_CCVP(base, 1)
54#define TIMER_CC1_CCVB(base) TIMER_CCx_CCVB(base, 1)
55
56#define TIMER_CC2_CTRL(base) TIMER_CCx_CTRL(base, 2)
57#define TIMER_CC2_CCV(base) TIMER_CCx_CCV(base, 2)
58#define TIMER_CC2_CCVP(base) TIMER_CCx_CCVP(base, 2)
59#define TIMER_CC2_CCVB(base) TIMER_CCx_CCVB(base, 2)
60
61#define TIMER_DTCTRL(base) MMIO32((base) + 0x070)
62#define TIMER_DTTIME(base) MMIO32((base) + 0x074)
63#define TIMER_DTFC(base) MMIO32((base) + 0x078)
64#define TIMER_DTOGEN(base) MMIO32((base) + 0x07C)
65#define TIMER_DTFAULT(base) MMIO32((base) + 0x080)
66#define TIMER_DTFAULTC(base) MMIO32((base) + 0x084)
67#define TIMER_DTLOCK(base) MMIO32((base) + 0x088)
68
69/* TIMER_CTRL */
70#define TIMER_CTRL_RSSCOIST (1 << 29)
71#define TIMER_CTRL_ATI (1 << 28)
72
73#define TIMER_CTRL_PRESC_SHIFT (24)
74#define TIMER_CTRL_PRESC_MASK (0xF << TIMER_CTRL_PRESC_SHIFT)
75#define TIMER_CTRL_PRESC(v) \
76 (((v) << TIMER_CTRL_PRESC_SHIFT) & TIMER_CTRL_PRESC_MASK)
77#define TIMER_CTRL_PRESC_DIV1 0
78#define TIMER_CTRL_PRESC_DIV2 1
79#define TIMER_CTRL_PRESC_DIV4 2
80#define TIMER_CTRL_PRESC_DIV8 3
81#define TIMER_CTRL_PRESC_DIV16 4
82#define TIMER_CTRL_PRESC_DIV32 5
83#define TIMER_CTRL_PRESC_DIV64 6
84#define TIMER_CTRL_PRESC_DIV128 7
85#define TIMER_CTRL_PRESC_DIV256 8
86#define TIMER_CTRL_PRESC_DIV512 9
87#define TIMER_CTRL_PRESC_DIV1024 10
88#define TIMER_CTRL_PRESC_NODIV TIMER_CTRL_PRESC_DIV1
89
90#define TIMER_CTRL_CLKSEL_SHIFT (16)
91#define TIMER_CTRL_CLKSEL_MASK (0x3 << TIMER_CTRL_CLKSEL_SHIFT)
92#define TIMER_CTRL_CLKSEL(v) \
93 (((v) << TIMER_CTRL_CLKSEL_SHIFT) & TIMER_CTRL_CLKSEL_MASK)
94#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0
95#define TIMER_CTRL_CLKSEL_CC1 1
96#define TIMER_CTRL_CLKSEL_TIMEROUF 2
97
98#define TIMER_CTRL_X2CNT (1 << 13)
99
100#define TIMER_CTRL_FALLA_SHIFT (10)
101#define TIMER_CTRL_FALLA_MASK (0x3 << TIMER_CTRL_FALLA_SHIFT)
102#define TIMER_CTRL_FALLA(v) \
103 (((v) << TIMER_CTRL_FALLA_SHIFT) & TIMER_CTRL_FALLA_MASK)
104#define TIMER_CTRL_FALLA_NONE 0
105#define TIMER_CTRL_FALLA_START 1
106#define TIMER_CTRL_FALLA_STOP 2
107#define TIMER_CTRL_FALLA_RELOADSTART 3
108
109#define TIMER_CTRL_RISEA_SHIFT (8)
110#define TIMER_CTRL_RISEA_MASK (0x3 << TIMER_CTRL_RISEA_SHIFT)
111#define TIMER_CTRL_RISEA(v) \
112 (((v) << TIMER_CTRL_RISEA_SHIFT) & TIMER_CTRL_RISEA_MASK)
113#define TIMER_CTRL_RISEA_NONE 0
114#define TIMER_CTRL_RISEA_START 1
115#define TIMER_CTRL_RISEA_STOP 2
116#define TIMER_CTRL_RISEA_RELOADSTART 3
117
118/* TIMER_CTRL_DMACLRACT bit is strangely documented.
119 * set this bit,
120 * in case you are doing one DMA transfer on every timer trigger event.
121 * if this bit is not set, strange behaviour is seen.
122*/
123
124#define TIMER_CTRL_DMACLRACT (1 << 7)
125#define TIMER_CTRL_DEBUGRUN (1 << 6)
126#define TIMER_CTRL_QDM (1 << 5)
127#define TIMER_CTRL_OSMEN (1 << 4)
128#define TIMER_CTRL_SYNC (1 << 3)
129
130#define TIMER_CTRL_MODE_SHIFT (0)
131#define TIMER_CTRL_MODE_MASK (0x3 << TIMER_CTRL_MODE_SHIFT)
132#define TIMER_CTRL_MODE(v) \
133 (((v) << TIMER_CTRL_MODE_SHIFT) & TIMER_CTRL_MODE_MASK)
134#define TIMER_CTRL_MODE_UP 0
135#define TIMER_CTRL_MODE_DOWN 1
136#define TIMER_CTRL_MODE_UPDOWN 2
137#define TIMER_CTRL_MODE_QDEC 3
138
139/* TIMER_CMD */
140#define TIMER_CMD_STOP (1 << 1)
141#define TIMER_CMD_START (1 << 0)
142
143/* TIMER_STATUS */
144#define TIMER_STATUS_CCPOLx(x) (1 << ((x) + 24))
145#define TIMER_STATUS_CCPOL2 TIMER_STATUS_CCPOLx(2)
146#define TIMER_STATUS_CCPOL1 TIMER_STATUS_CCPOLx(1)
147#define TIMER_STATUS_CCPOL0 TIMER_STATUS_CCPOLx(0)
148
149#define TIMER_STATUS_ICVx(x) (1 << ((x) + 16))
150#define TIMER_STATUS_ICV2 TIMER_STATUS_ICVx(2)
151#define TIMER_STATUS_ICV1 TIMER_STATUS_ICVx(1)
152#define TIMER_STATUS_ICV0 TIMER_STATUS_ICVx(0)
153
154#define TIMER_STATUS_CCVBVx(x) (1 << ((x) + 8))
155#define TIMER_STATUS_CCVBV2 TIMER_STATUS_CCVBVx(2)
156#define TIMER_STATUS_CCVBV1 TIMER_STATUS_CCVBVx(1)
157#define TIMER_STATUS_CCVBV0 TIMER_STATUS_CCVBVx(0)
158
159#define TIMER_STATUS_TOPBV (1 << 2)
160#define TIMER_STATUS_DIR (1 << 1)
161#define TIMER_STATUS_RUNNING (1 << 0)
162
163/* TIMER_IEN */
164#define TIMER_IEN_ICBOFx(x) (1 << ((x) + 8))
165#define TIMER_IEN_ICBOF0 TIMER_IEN_ICBOFx(0)
166#define TIMER_IEN_ICBOF1 TIMER_IEN_ICBOFx(1)
167#define TIMER_IEN_ICBOF2 TIMER_IEN_ICBOFx(2)
168
169#define TIMER_IEN_CCx(x) (1 << ((x) + 4))
170#define TIMER_IEN_CC0 TIMER_IEN_CCx(0)
171#define TIMER_IEN_CC1 TIMER_IEN_CCx(1)
172#define TIMER_IEN_CC2 TIMER_IEN_CCx(2)
173
174#define TIMER_IEN_UF (1 << 1)
175#define TIMER_IEN_OF (1 << 0)
176
177
178/* TIMER_IF */
179#define TIMER_IF_ICBOFx(x) (1 << ((x) + 8))
180#define TIMER_IF_ICBOF0 TIMER_IF_ICBOFx(0)
181#define TIMER_IF_ICBOF1 TIMER_IF_ICBOFx(1)
182#define TIMER_IF_ICBOF2 TIMER_IF_ICBOFx(2)
183
184#define TIMER_IF_CCx(x) (1 << ((x) + 4))
185#define TIMER_IF_CC0 TIMER_IF_CCx(0)
186#define TIMER_IF_CC1 TIMER_IF_CCx(1)
187#define TIMER_IF_CC2 TIMER_IF_CCx(2)
188
189#define TIMER_IF_UF (1 << 1)
190#define TIMER_IF_OF (1 << 0)
191
192/* TIMER_IFS */
193#define TIMER_IFS_ICBOFx(x) (1 << ((x) + 8))
194#define TIMER_IFS_ICBOF0 TIMER_IFS_ICBOFx(0)
195#define TIMER_IFS_ICBOF1 TIMER_IFS_ICBOFx(1)
196#define TIMER_IFS_ICBOF2 TIMER_IFS_ICBOFx(2)
197
198#define TIMER_IFS_CCx(x) (1 << ((x) + 4))
199#define TIMER_IFS_CC0 TIMER_IFS_CCx(0)
200#define TIMER_IFS_CC1 TIMER_IFS_CCx(1)
201#define TIMER_IFS_CC2 TIMER_IFS_CCx(2)
202
203#define TIMER_IFS_UF (1 << 1)
204#define TIMER_IFS_OF (1 << 0)
205
206
207/* TIMER_IFC */
208#define TIMER_IFC_ICBOFx(x) (1 << ((x) + 8))
209#define TIMER_IFC_ICBOF0 TIMER_IFC_ICBOFx(0)
210#define TIMER_IFC_ICBOF1 TIMER_IFC_ICBOFx(1)
211#define TIMER_IFC_ICBOF2 TIMER_IFC_ICBOFx(2)
212
213#define TIMER_IFC_CCx(x) (1 << ((x) + 4))
214#define TIMER_IFC_CC0 TIMER_IFC_CCx(0)
215#define TIMER_IFC_CC1 TIMER_IFC_CCx(1)
216#define TIMER_IFC_CC2 TIMER_IFC_CCx(2)
217
218#define TIMER_IFC_UF (1 << 1)
219#define TIMER_IFC_OF (1 << 0)
220
221/* TIMER_ROUTE */
222#define TIMER_ROUTE_LOCATION_SHIFT (16)
223#define TIMER_ROUTE_LOCATION_MASK (0x7 << TIMER_ROUTE_LOCATION_SHIFT)
224#define TIMER_ROUTE_LOCATION(v) \
225 (((v) << TIMER_ROUTE_LOCATION_SHIFT) & TIMER_ROUTE_LOCATION_MASK)
226#define TIMER_ROUTE_LOCATION_LOCx(x) TIMER_ROUTE_LOCATION(x)
227#define TIMER_ROUTE_LOCATION_LOC0 0
228#define TIMER_ROUTE_LOCATION_LOC1 1
229#define TIMER_ROUTE_LOCATION_LOC2 2
230#define TIMER_ROUTE_LOCATION_LOC3 3
231#define TIMER_ROUTE_LOCATION_LOC4 4
232#define TIMER_ROUTE_LOCATION_LOC5 5
233
234#define TIMER_ROUTE_CDTIxPEN(x) (1 << (8 + (x)))
235#define TIMER_ROUTE_CDTI0PEN TIMER_ROUTE_CDTIxPEN(0)
236#define TIMER_ROUTE_CDTI1PEN TIMER_ROUTE_CDTIxPEN(1)
237#define TIMER_ROUTE_CDTI2PEN TIMER_ROUTE_CDTIxPEN(2)
238
239#define TIMER_ROUTE_CCxPEN(x) (1 << (0 + (x)))
240#define TIMER_ROUTE_CC0PEN TIMER_ROUTE_CCxPEN(0)
241#define TIMER_ROUTE_CC1PEN TIMER_ROUTE_CCxPEN(1)
242#define TIMER_ROUTE_CC2PEN TIMER_ROUTE_CCxPEN(2)
243
244/* TIMER_CCx_CTRL */
245#define TIMER_CC_CTRL_ICEVCTRL_SHIFT (26)
246#define TIMER_CC_CTRL_ICEVCTRL_MASK (0x3 << TIMER_CC_CTRL_ICEVCTRL_SHIFT)
247#define TIMER_CC_CTRL_ICEVCTRL(v) \
248 (((v) << TIMER_CC_CTRL_ICEVCTRL_SHIFT) & TIMER_CC_CTRL_ICEVCTRL_MASK)
249#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0
250#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 1
251#define TIMER_CC_CTRL_ICEVCTRL_RISING 2
252#define TIMER_CC_CTRL_ICEVCTRL_FALLING 3
253
254#define TIMER_CC_CTRL_ICEVCTRL_EVERY_EDGE \
255 TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE
256#define TIMER_CC_CTRL_ICEVCTRL_EVERY_SECOND_EDGE \
257 TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE
258
259#define TIMER_CC_CTRL_ICEDGE_SHIFT (24)
260#define TIMER_CC_CTRL_ICEDGE_MASK (0x3 << TIMER_CC_CTRL_ICEDGE_SHIFT)
261#define TIMER_CC_CTRL_ICEDGE(v) \
262 (((v) << TIMER_CC_CTRL_ICEDGE_SHIFT) & TIMER_CC_CTRL_ICEDGE_MASK)
263#define TIMER_CC_CTRL_ICEDGE_RISING 0
264#define TIMER_CC_CTRL_ICEDGE_FALLING 1
265#define TIMER_CC_CTRL_ICEDGE_BOTH 2
266#define TIMER_CC_CTRL_ICEDGE_NONE 3
267
268#define TIMER_CC_CTRL_FILT (1 << 21)
269#define TIMER_CC_CTRL_INSEL (1 << 21)
270
271
272#define TIMER_CC_CTRL_PRSSEL_SHIFT (16)
273#define TIMER_CC_CTRL_PRSSEL_MASK (0xF << TIMER_CC_CTRL_PRSSEL_SHIFT)
274#define TIMER_CC_CTRL_PRSSEL(v) \
275 (((v) << TIMER_CC_CTRL_PRSSEL_SHIFT) & TIMER_CC_CTRL_PRSSEL_MASK)
276#define TIMER_CC_CTRL_PRSSEL_PRSCHx(x) TIMER_CC_CTRL_PRSSEL(x)
277#define TIMER_CC_CTRL_PRSSEL_PRSCH0 0
278#define TIMER_CC_CTRL_PRSSEL_PRSCH1 1
279#define TIMER_CC_CTRL_PRSSEL_PRSCH2 2
280#define TIMER_CC_CTRL_PRSSEL_PRSCH3 3
281#define TIMER_CC_CTRL_PRSSEL_PRSCH4 4
282#define TIMER_CC_CTRL_PRSSEL_PRSCH5 5
283#define TIMER_CC_CTRL_PRSSEL_PRSCH6 6
284#define TIMER_CC_CTRL_PRSSEL_PRSCH7 7
285#define TIMER_CC_CTRL_PRSSEL_PRSCH8 8
286#define TIMER_CC_CTRL_PRSSEL_PRSCH9 9
287#define TIMER_CC_CTRL_PRSSEL_PRSCH10 10
288#define TIMER_CC_CTRL_PRSSEL_PRSCH11 11
289
290#define TIMER_CC_CTRL_CUFOA_SHIFT (12)
291#define TIMER_CC_CTRL_CUFOA_MASK (0x3 << TIMER_CC_CTRL_CUFOA_SHIFT)
292#define TIMER_CC_CTRL_CUFOA(v) \
293 (((v) << TIMER_CC_CTRL_CUFOA_SHIFT) & TIMER_CC_CTRL_CUFOA_MASK)
294#define TIMER_CC_CTRL_CUFOA_NONE 0
295#define TIMER_CC_CTRL_CUFOA_TOGGLE 1
296#define TIMER_CC_CTRL_CUFOA_CLEAR 2
297#define TIMER_CC_CTRL_CUFOA_SET 3
298
299#define TIMER_CC_CTRL_COFOA_SHIFT (10)
300#define TIMER_CC_CTRL_COFOA_MASK (0x3 << TIMER_CC_CTRL_COFOA_SHIFT)
301#define TIMER_CC_CTRL_COFOA(v) \
302 (((v) << TIMER_CC_CTRL_COFOA_SHIFT) & TIMER_CC_CTRL_COFOA_MASK)
303#define TIMER_CC_CTRL_COFOA_NONE 0
304#define TIMER_CC_CTRL_COFOA_TOGGLE 1
305#define TIMER_CC_CTRL_COFOA_CLEAR 2
306#define TIMER_CC_CTRL_COFOA_SET 3
307
308#define TIMER_CC_CTRL_CMOA_SHIFT (8)
309#define TIMER_CC_CTRL_CMOA_MASK (0x3 << TIMER_CC_CTRL_CMOA_SHIFT)
310#define TIMER_CC_CTRL_CMOA(v) \
311 (((v) << TIMER_CC_CTRL_CMOA_SHIFT) & TIMER_CC_CTRL_CMOA_MASK)
312#define TIMER_CC_CTRL_CMOA_NONE 0
313#define TIMER_CC_CTRL_CMOA_TOGGLE 1
314#define TIMER_CC_CTRL_CMOA_CLEAR 2
315#define TIMER_CC_CTRL_CMOA_SET 3
316
317#define TIMER_CC_CTRL_COIST (1 << 4)
318#define TIMER_CC_CTRL_OUTINV (1 << 2)
319
320#define TIMER_CC_CTRL_MODE_SHIFT (0)
321#define TIMER_CC_CTRL_MODE_MASK (0x3 << TIMER_CC_CTRL_MODE_SHIFT)
322#define TIMER_CC_CTRL_MODE(v) \
323 (((v) << TIMER_CC_CTRL_MODE_SHIFT) & TIMER_CC_CTRL_MODE_MASK)
324#define TIMER_CC_CTRL_MODE_OFF 0
325#define TIMER_CC_CTRL_MODE_INPUTCAPTURE 1
326#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 2
327#define TIMER_CC_CTRL_MODE_PWM 3
328
329#define TIMER_CC_CTRL_MODE_INPUT_CAPTURE \
330 TIMER_CC_CTRL_MODE_INPUTCAPTURE
331#define TIMER_CC_CTRL_MODE_OUTPUT_CAPTURE \
332 TIMER_CC_CTRL_MODE_OUTPUTCAPTURE
333
334/* TIMER_DTCTRL */
335#define TIMER_DTCTRL_DTPRSEN (1 << 24)
336
337#define TIMER_DTCTRL_DTPRSSEL_SHIFT (4)
338#define TIMER_DTCTRL_DTPRSSEL_MASK (0xF << TIMER_DTCTRL_DTPRSSEL_SHIFT)
339#define TIMER_DTCTRL_DTPRSSEL(v) \
340 (((v) << TIMER_DTCTRL_DTPRSSEL_SHIFT) & TIMER_DTCTRL_DTPRSSEL_MASK)
341#define TIMER_DTCTRL_DTPRSSEL_PRSCHx(x) TIMER_DTCTRL_DTPRSSEL(x)
342#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 0
343#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 1
344#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 2
345#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 3
346#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 4
347#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 5
348#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 6
349#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 7
350#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 8
351#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 9
352#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 10
353#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 11
354
355#define TIMER_DTCTRL_DTCINV (1 << 3)
356#define TIMER_DTCTRL_DTIPOL (1 << 2)
357#define TIMER_DTCTRL_DTDAS (1 << 1)
358#define TIMER_DTCTRL_DTEN (1 << 0)
359
360/* TIMER_DTTIME */
361#define TIMER_DTTIME_DTFALLT_SHIFT (16)
362#define TIMER_DTTIME_DTFALLT_MASK (0x3F << TIMER_DTTIME_DTFALLT_SHIFT)
363#define TIMER_DTTIME_DTFALLT(v) \
364 (((v) << TIMER_DTTIME_DTFALLT_SHIFT) & TIMER_DTTIME_DTFALLT_MASK)
365
366#define TIMER_DTTIME_DTRISET_SHIFT (8)
367#define TIMER_DTTIME_DTRISET_MASK (0x3F << TIMER_DTTIME_DTRISET_SHIFT)
368#define TIMER_DTTIME_DTRISET(v) \
369 (((v) << TIMER_DTTIME_DTRISET_SHIFT) & TIMER_DTTIME_DTRISET_MASK)
370
371
372#define TIMER_DTTIME_DTPRESC_SHIFT (0)
373#define TIMER_DTTIME_DTPRESC_MASK (0xF << TIMER_DTTIME_DTPRESC_SHIFT)
374#define TIMER_DTTIME_DTPRESC(v) \
375 (((v) << TIMER_DTTIME_DTPRESC_SHIFT) & TIMER_DTTIME_DTPRESC_MASK)
376#define TIMER_DTTIME_DTPRESC_DIV1 0
377#define TIMER_DTTIME_DTPRESC_DIV2 1
378#define TIMER_DTTIME_DTPRESC_DIV4 2
379#define TIMER_DTTIME_DTPRESC_DIV8 3
380#define TIMER_DTTIME_DTPRESC_DIV16 4
381#define TIMER_DTTIME_DTPRESC_DIV32 5
382#define TIMER_DTTIME_DTPRESC_DIV64 6
383#define TIMER_DTTIME_DTPRESC_DIV128 7
384#define TIMER_DTTIME_DTPRESC_DIV256 8
385#define TIMER_DTTIME_DTPRESC_DIV512 8
386#define TIMER_DTTIME_DTPRESC_DIV1024 10
387#define TIMER_DTTIME_DTPRESC_NODIV TIMER_DTTIME_DTPRESC_DIV1
388
389/* TIMER_DTFC */
390#define TIMER_DTFC_DTLOCKUPFEN (1 << 27)
391#define TIMER_DTFC_DTDBGFEN (1 << 26)
392#define TIMER_DTFC_DTPRS1FEN (1 << 25)
393#define TIMER_DTFC_DTPRS0FEN (1 << 24)
394
395#define TIMER_DTFC_DTFA_SHIFT (16)
396#define TIMER_DTFC_DTFA_MASK (0x3 << TIMER_DTFC_DTFA_SHIFT)
397#define TIMER_DTFC_DTFA(v) \
398 (((v) << TIMER_DTFC_DTFA_SHIFT) & TIMER_DTFC_DTFA_MASK)
399#define TIMER_DTFC_DTFA_NONE 0
400#define TIMER_DTFC_DTFA_INACTIVE 1
401#define TIMER_DTFC_DTFA_CLEAR 2
402#define TIMER_DTFC_DTFA_TRISTATE 3
403
404#define TIMER_DTFC_DTPRS1FSEL_SHIFT (8)
405#define TIMER_DTFC_DTPRS1FSEL_MASK (0x3 << TIMER_DTFC_DTPRS1FSEL_SHIFT)
406#define TIMER_DTFC_DTPRS1FSEL(v) \
407 (((v) << TIMER_DTFC_DTPRS1FSEL_SHIFT) & TIMER_DTFC_DTPRS1FSEL_MASK)
408#define TIMER_DTFC_DTPRS1FSEL_PRSCHx(x) TIMER_DTFC_DTPRS1FSEL(x)
409#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 0
410#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 1
411#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 2
412#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 3
413#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 4
414#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 5
415#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 6
416#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 7
417
418#define TIMER_DTFC_DTPRS0FSEL_SHIFT (8)
419#define TIMER_DTFC_DTPRS0FSEL_MASK (0x3 << TIMER_DTFC_DTPRS0FSEL_SHIFT)
420#define TIMER_DTFC_DTPRS0FSEL(v) \
421 (((v) << TIMER_DTFC_DTPRS0FSEL_SHIFT) & TIMER_DTFC_DTPRS0FSEL_MASK)
422#define TIMER_DTFC_DTPRS0FSEL_PRSCHx(x) TIMER_DTFC_DTPRS0FSEL(x)
423#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 0
424#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 1
425#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 2
426#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 3
427#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 4
428#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 5
429#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 6
430#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 7
431
432/* TIMER_DTOGEN */
433#define TIMER_DTOGEN_DTOGCDTI2EN (1 << 5)
434#define TIMER_DTOGEN_DTOGCDTI1EN (1 << 4)
435#define TIMER_DTOGEN_DTOGCDTI0EN (1 << 3)
436#define TIMER_DTOGEN_DTOGCC2EN (1 << 2)
437#define TIMER_DTOGEN_DTOGCC1EN (1 << 1)
438#define TIMER_DTOGEN_DTOGCC0EN (1 << 0)
439
440/* TIMER_DTFAULT */
441#define TIMER_DTFAULT_DTLOCKUPF (1 << 3)
442#define TIMER_DTFAULT_DTDBGF (1 << 2)
443#define TIMER_DTFAULT_DTPRS1F (1 << 1)
444#define TIMER_DTFAULT_DTPRS0F (1 << 0)
445
446/* TIMER_DTFAULTC */
447#define TIMER_DTFAULTC_TLOCKUPFC (1 << 3)
448#define TIMER_DTFAULTC_DTDBGFC (1 << 2)
449#define TIMER_DTFAULTC_DTPRS1FC (1 << 1)
450#define TIMER_DTFAULTC_DTPRS0FC (1 << 0)
451
452/* TIMER_DTLOCK */
453#define TIMER_DTLOCK_LOCKKEY_SHIFT (0)
454#define TIMER_DTLOCK_LOCKKEY_MASK (0xFFFF << TIMER_DTLOCK_LOCKKEY_SHIFT)
455#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (0x0000 << TIMER_DTLOCK_LOCKKEY_SHIFT)
456#define TIMER_DTLOCK_LOCKKEY_LOCKED (0x0001 << TIMER_DTLOCK_LOCKKEY_SHIFT)
457#define TIMER_DTLOCK_LOCKKEY_LOCK (0x0000 << TIMER_DTLOCK_LOCKKEY_SHIFT)
458#define TIMER_DTLOCK_LOCKKEY_UNLOCK (0xCE80 << TIMER_DTLOCK_LOCKKEY_SHIFT)
459
460/* TIMER0 */
461#define TIMER0 TIMER0_BASE
462#define TIMER0_CTRL TIMER_CTRL(TIMER0)
463#define TIMER0_CMD TIMER_CMD(TIMER0)
464#define TIMER0_STATUS TIMER_STATUS(TIMER0)
465#define TIMER0_IEN TIMER_IEN(TIMER0)
466#define TIMER0_IF TIMER_IF(TIMER0)
467#define TIMER0_IFS TIMER_IFS(TIMER0)
468#define TIMER0_IFC TIMER_IFC(TIMER0)
469#define TIMER0_TOP TIMER_TOP(TIMER0)
470#define TIMER0_TOPB TIMER_TOPB(TIMER0)
471#define TIMER0_CNT TIMER_CNT(TIMER0)
472#define TIMER0_ROUTE TIMER_ROUTE(TIMER0)
473
474#define TIMER0_CC0_CTRL TIMER_CC0_CTRL(TIMER0)
475#define TIMER0_CC0_CCV TIMER_CC0_CCV(TIMER0)
476#define TIMER0_CC0_CCVP TIMER_CC0_CCVP(TIMER0)
477#define TIMER0_CC0_CCVB TIMER_CC0_CCVB(TIMER0)
478
479#define TIMER0_CC1_CTRL TIMER_CC1_CTRL(TIMER0)
480#define TIMER0_CC1_CCV TIMER_CC1_CCV(TIMER0)
481#define TIMER0_CC1_CCVP TIMER_CC1_CCVP(TIMER0)
482#define TIMER0_CC1_CCVB TIMER_CC1_CCVB(TIMER0)
483
484#define TIMER0_CC2_CTRL TIMER_CC2_CTRL(TIMER0)
485#define TIMER0_CC2_CCV TIMER_CC2_CCV(TIMER0)
486#define TIMER0_CC2_CCVP TIMER_CC2_CCVP(TIMER0)
487#define TIMER0_CC2_CCVB TIMER_CC2_CCVB(TIMER0)
488
489#define TIMER0_DTCTRL TIMER_DTCTRL(TIMER0)
490#define TIMER0_DTTIME TIMER_DTTIME(TIMER0)
491#define TIMER0_DTFC TIMER_DTFC(TIMER0)
492#define TIMER0_DTOGEN TIMER_DTOGEN(TIMER0)
493#define TIMER0_DTFAULT TIMER_DTFAULT(TIMER0)
494#define TIMER0_DTFAULTC TIMER_DTFAULTC(TIMER0)
495#define TIMER0_DTLOCK TIMER_DTLOCK(TIMER0)
496
497/* TIMER1 */
498#define TIMER1 TIMER1_BASE
499#define TIMER1_CTRL TIMER_CTRL(TIMER1)
500#define TIMER1_CMD TIMER_CMD(TIMER1)
501#define TIMER1_STATUS TIMER_STATUS(TIMER1)
502#define TIMER1_IEN TIMER_IEN(TIMER1)
503#define TIMER1_IF TIMER_IF(TIMER1)
504#define TIMER1_IFS TIMER_IFS(TIMER1)
505#define TIMER1_IFC TIMER_IFC(TIMER1)
506#define TIMER1_TOP TIMER_TOP(TIMER1)
507#define TIMER1_TOPB TIMER_TOPB(TIMER1)
508#define TIMER1_CNT TIMER_CNT(TIMER1)
509#define TIMER1_ROUTE TIMER_ROUTE(TIMER1)
510
511#define TIMER1_CC0_CTRL TIMER_CC0_CTRL(TIMER1)
512#define TIMER1_CC0_CCV TIMER_CC0_CCV(TIMER1)
513#define TIMER1_CC0_CCVP TIMER_CC0_CCVP(TIMER1)
514#define TIMER1_CC0_CCVB TIMER_CC0_CCVB(TIMER1)
515
516#define TIMER1_CC1_CTRL TIMER_CC1_CTRL(TIMER1)
517#define TIMER1_CC1_CCV TIMER_CC1_CCV(TIMER1)
518#define TIMER1_CC1_CCVP TIMER_CC1_CCVP(TIMER1)
519#define TIMER1_CC1_CCVB TIMER_CC1_CCVB(TIMER1)
520
521#define TIMER1_CC2_CTRL TIMER_CC2_CTRL(TIMER1)
522#define TIMER1_CC2_CCV TIMER_CC2_CCV(TIMER1)
523#define TIMER1_CC2_CCVP TIMER_CC2_CCVP(TIMER1)
524#define TIMER1_CC2_CCVB TIMER_CC2_CCVB(TIMER1)
525
526/* TIMER2 */
527#define TIMER2 TIMER2_BASE
528#define TIMER2_CTRL TIMER_CTRL(TIMER2)
529#define TIMER2_CMD TIMER_CMD(TIMER2)
530#define TIMER2_STATUS TIMER_STATUS(TIMER2)
531#define TIMER2_IEN TIMER_IEN(TIMER2)
532#define TIMER2_IF TIMER_IF(TIMER2)
533#define TIMER2_IFS TIMER_IFS(TIMER2)
534#define TIMER2_IFC TIMER_IFC(TIMER2)
535#define TIMER2_TOP TIMER_TOP(TIMER2)
536#define TIMER2_TOPB TIMER_TOPB(TIMER2)
537#define TIMER2_CNT TIMER_CNT(TIMER2)
538#define TIMER2_ROUTE TIMER_ROUTE(TIMER2)
539
540#define TIMER2_CC0_CTRL TIMER_CC0_CTRL(TIMER2)
541#define TIMER2_CC0_CCV TIMER_CC0_CCV(TIMER2)
542#define TIMER2_CC0_CCVP TIMER_CC0_CCVP(TIMER2)
543#define TIMER2_CC0_CCVB TIMER_CC0_CCVB(TIMER2)
544
545#define TIMER2_CC1_CTRL TIMER_CC1_CTRL(TIMER2)
546#define TIMER2_CC1_CCV TIMER_CC1_CCV(TIMER2)
547#define TIMER2_CC1_CCVP TIMER_CC1_CCVP(TIMER2)
548#define TIMER2_CC1_CCVB TIMER_CC1_CCVB(TIMER2)
549
550#define TIMER2_CC2_CTRL TIMER_CC2_CTRL(TIMER2)
551#define TIMER2_CC2_CCV TIMER_CC2_CCV(TIMER2)
552#define TIMER2_CC2_CCVP TIMER_CC2_CCVP(TIMER2)
553#define TIMER2_CC2_CCVB TIMER_CC2_CCVB(TIMER2)
554
555/* TIMER3 */
556#define TIMER3 TIMER3_BASE
557#define TIMER3_CTRL TIMER_CTRL(TIMER3)
558#define TIMER3_CMD TIMER_CMD(TIMER3)
559#define TIMER3_STATUS TIMER_STATUS(TIMER3)
560#define TIMER3_IEN TIMER_IEN(TIMER3)
561#define TIMER3_IF TIMER_IF(TIMER3)
562#define TIMER3_IFS TIMER_IFS(TIMER3)
563#define TIMER3_IFC TIMER_IFC(TIMER3)
564#define TIMER3_TOP TIMER_TOP(TIMER3)
565#define TIMER3_TOPB TIMER_TOPB(TIMER3)
566#define TIMER3_CNT TIMER_CNT(TIMER3)
567#define TIMER3_ROUTE TIMER_ROUTE(TIMER3)
568
569#define TIMER3_CC0_CTRL TIMER_CC0_CTRL(TIMER3)
570#define TIMER3_CC0_CCV TIMER_CC0_CCV(TIMER3)
571#define TIMER3_CC0_CCVP TIMER_CC0_CCVP(TIMER3)
572#define TIMER3_CC0_CCVB TIMER_CC0_CCVB(TIMER3)
573
574#define TIMER3_CC1_CTRL TIMER_CC1_CTRL(TIMER3)
575#define TIMER3_CC1_CCV TIMER_CC1_CCV(TIMER3)
576#define TIMER3_CC1_CCVP TIMER_CC1_CCVP(TIMER3)
577#define TIMER3_CC1_CCVB TIMER_CC1_CCVB(TIMER3)
578
579#define TIMER3_CC2_CTRL TIMER_CC2_CTRL(TIMER3)
580#define TIMER3_CC2_CCV TIMER_CC2_CCV(TIMER3)
581#define TIMER3_CC2_CCVP TIMER_CC2_CCVP(TIMER3)
582#define TIMER3_CC2_CCVB TIMER_CC2_CCVB(TIMER3)
583
584/** @defgroup timer_ch Timer Channel Number
585@ingroup timer_defines
586
587@{*/
588enum tim_ch {
591 TIM_CH2
593/**@}*/
594
596
597void timer_start(uint32_t timer);
598void timer_stop(uint32_t timer);
599
600void timer_set_clock_prescaler(uint32_t timer, uint32_t prescaler);
601
602void timer_set_top(uint32_t timer, uint32_t top);
603
604/* TODO: interrupt {enable, disable, read-flags} */
605
606/* TODO: for channel (output value, input value)
607 * enable channel
608 * set location, set output mode */
609
611
612/**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
Dispatcher for the base address definitions, depending on the particular Gecko family.
tim_ch
Definition: timer_common.h:588
@ TIM_CH0
Definition: timer_common.h:589
@ TIM_CH1
Definition: timer_common.h:590
@ TIM_CH2
Definition: timer_common.h:591
void timer_set_clock_prescaler(uint32_t timer, uint32_t prescaler)
Clock division factor.
Definition: timer_common.c:52
void timer_set_top(uint32_t timer, uint32_t top)
Start timer top value the timer reload after it reaches top value.
Definition: timer_common.c:64
void timer_start(uint32_t timer)
Start timer.
Definition: timer_common.c:33
void timer_stop(uint32_t timer)
Stop timer.
Definition: timer_common.c:42