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#define | EMU_CTRL MMIO32(EMU_BASE + 0x000) |
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#define | EMU_LOCK MMIO32(EMU_BASE + 0x008) |
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#define | EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) |
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#define | EMU_EM4CONF MMIO32(EMU_BASE + 0x02C) |
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#define | EMU_BUCTRL MMIO32(EMU_BASE + 0x030) |
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#define | EMU_PWRCONF MMIO32(EMU_BASE + 0x034) |
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#define | EMU_BUINACT MMIO32(EMU_BASE + 0x038) |
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#define | EMU_BUACT MMIO32(EMU_BASE + 0x03C) |
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#define | EMU_STATUS MMIO32(EMU_BASE + 0x040) |
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#define | EMU_ROUTE MMIO32(EMU_BASE + 0x044) |
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#define | EMU_IF MMIO32(EMU_BASE + 0x048) |
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#define | EMU_IFS MMIO32(EMU_BASE + 0x04C) |
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#define | EMU_IFC MMIO32(EMU_BASE + 0x050) |
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#define | EMU_IEN MMIO32(EMU_BASE + 0x054) |
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#define | EMU_BUBODBUVINCAL MMIO32(EMU_BASE + 0x058) |
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#define | EMU_BUBODUNREGCAL MMIO32(EMU_BASE + 0x05C) |
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#define | EMU_CTRL_EM4CTRL_SHIFT (2) |
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#define | EMU_CTRL_EM4CTRL_MASK (0x3 << EMU_CTRL_EM4CTRL_SHIFT) |
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#define | EMU_CTLR_EM4CTRL(v) (((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK) |
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#define | EMU_CTRL_EM2BLOCK (1 << 1) |
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#define | EMU_CTRL_EMVREG (1 << 0) |
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#define | EMU_LOCK_LOCKKEY_MASK (0xFFFF) |
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#define | EMU_LOCK_LOCKKEY_LOCK (0) |
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#define | EMU_LOCK_LOCKKEY_UNLOCK (0xADE8) |
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#define | EMU_AUXCTRL_HRCCLR (1 << 0) |
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#define | EMU_EM4CONF_LOCKCONF (1 << 16) |
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#define | EMU_EM4CONF_BUBODRSTDIS (1 << 4) |
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#define | EMU_EM4CONF_OSC_SHIFT (2) |
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#define | EMU_EM4CONF_OSC_MASK (0x3 << EMU_EM4CONF_OSC_SHIFT) |
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#define | EMU_EM4CONF_OSC(v) (((v) << EMU_EM4CONF_OSC_SHIFT) & EMU_EM4CONF_OSC_MASK) |
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#define | EMU_EM4CONF_OSC_ULFRCO 0 |
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#define | EMU_EM4CONF_OSC_LFRCO 1 |
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#define | EMU_EM4CONF_OSC_LFXO 2 |
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#define | EMU_EM4CONF_BURTCWU (1 << 1) |
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#define | EMU_EM4CONF_VREGEN (1 << 0) |
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#define | EMU_BUCTRL_PROBE_SHIFT (5) |
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#define | EMU_BUCTRL_PROBE_MASK (0x3 << EMU_BUCTRL_PROBE_SHIFT) |
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#define | EMU_BUCTRL_PROBE(v) (((v) << EMU_BUCTRL_PROBE_SHIFT) & EMU_BUCTRL_PROBE_MASK) |
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#define | EMU_BUCTRL_PROBE_DISABLE 0 |
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#define | EMU_BUCTRL_PROBE_VDDDREG 1 |
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#define | EMU_BUCTRL_PROBE_BUIN 2 |
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#define | EMU_BUCTRL_PROBE_BUOUT 3 |
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#define | EMU_BUCTRL_BUMODEBODEN (1 << 3) |
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#define | EMU_BUCTRL_BODCAL (1 << 2) |
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#define | EMU_BUCTRL_STATEN (1 << 1) |
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#define | EMU_BUCTRL_EN (1 << 0) |
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#define | EMU_PWRCONF_PWRRES_SHIFT (3) |
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#define | EMU_PWRCONF_PWRRES_MASK (0x3 << EMU_PWRCONF_PWRRES_SHIFT) |
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#define | EMU_PWRCONF_PWRRES(v) (((v) << EMU_PWRCONF_PWRRES_SHIFT) & EMU_PWRCONF_PWRRES_MASK) |
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#define | EMU_PWRCONF_PWRRES_DISABLE 0 |
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#define | EMU_PWRCONF_PWRRES_VDDDREG 1 |
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#define | EMU_PWRCONF_PWRRES_BUIN 2 |
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#define | EMU_PWRCONF_PWRRES_BUOUT 3 |
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#define | EMU_PWRCONF_VOUTSTRONG (1 << 2) |
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#define | EMU_PWRCONF_VOUTMED (1 << 1) |
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#define | EMU_PWRCONF_VOUTWEAK (1 << 0) |
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#define | EMU_BUINACT_PWRCON_SHIFT (5) |
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#define | EMU_BUINACT_PWRCON_MASK (0x3 << EMU_BUINACT_PWRCON_SHIFT) |
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#define | EMU_BUINACT_PWRCON(v) (((v) << EMU_BUINACT_PWRCON_SHIFT) & EMU_BUINACT_PWRCON_MASK) |
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#define | EMU_BUINACT_PWRCON_NONE 0 |
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#define | EMU_BUINACT_PWRCON_BUMAIN 1 |
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#define | EMU_BUINACT_PWRCON_MAINBU 2 |
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#define | EMU_BUINACT_PWRCON_NODIODE 3 |
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#define | EMU_BUINACT_BUENRANGE_SHIFT (3) |
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#define | EMU_BUINACT_BUENRANGE_MASK (0x3 << EMU_BUINACT_BUENRANGE_SHIFT) |
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#define | EMU_BUINACT_BUENRANGE(v) (((v) << EMU_BUINACT_BUENRANGE_SHIFT) & EMU_BUINACT_BUENRANGE_MASK) |
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#define | EMU_BUINACT_BUENTHRES_SHIFT (0) |
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#define | EMU_BUINACT_BUENTHRES_MASK (0x7 << EMU_BUINACT_BUENTHRES_SHIFT) |
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#define | EMU_BUINACT_BUENTHRES(v) (((v) << EMU_BUINACT_BUENTHRES_SHIFT) & EMU_BUINACT_BUENTHRES_MASK) |
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#define | EMU_BUACT_PWRCON_SHIFT (5) |
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#define | EMU_BUACT_PWRCON_MASK (0x3 << EMU_BUACT_PWRCON_SHIFT) |
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#define | EMU_BUACT_PWRCON(v) (((v) << EMU_BUACT_PWRCON_SHIFT) & EMU_BUACT_PWRCON_MASK) |
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#define | EMU_BUACT_PWRCON_NONE 0 |
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#define | EMU_BUACT_PWRCON_BUMAIN 1 |
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#define | EMU_BUACT_PWRCON_MAINBU 2 |
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#define | EMU_BUACT_PWRCON_NODIODE 3 |
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#define | EMU_BUACT_BUEXRANGE_SHIFT (3) |
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#define | EMU_BUACT_BUEXRANGE_MASK (0x3 << EMU_BUACT_BUEXRANGE_SHIFT) |
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#define | EMU_BUACT_BUEXRANGE(v) (((v) << EMU_BUACT_BUEXRANGE_SHIFT) & EMU_BUACT_BUEXRANGE_MASK) |
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#define | EMU_BUACT_BUEXTHRES_SHIFT (0) |
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#define | EMU_BUACT_BUEXTHRES_MASK (0x7 << EMU_BUACT_BUEXTHRES_SHIFT) |
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#define | EMU_BUACT_BUEXTHRES(v) (((v) << EMU_BUACT_BUEXTHRES_SHIFT) & EMU_BUACT_BUEXTHRES_MASK) |
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#define | EMU_STATUS_BURDY (1 << 0) |
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#define | EMU_ROUTE_BUVINPEN (1 << 0) |
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#define | EMU_IF_BURDY (1 << 0) |
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#define | EMU_IFS_BURDY (1 << 0) |
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#define | EMU_IFC_BURDY (1 << 0) |
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#define | EMU_IEN_BURDY (1 << 0) |
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#define | EMU_BUBODBUVINCAL_RANGE_SHIFT (3) |
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#define | EMU_BUBODBUVINCAL_RANGE_MASK (0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT) |
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#define | EMU_BUBODBUVINCAL_RANGE(v) |
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#define | EMU_BUBODBUVINCAL_THRES_SHIFT (0) |
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#define | EMU_BUBODBUVINCAL_THRES_MASK (0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT) |
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#define | EMU_BUBODBUVINCAL_THRES(v) |
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#define | EMU_BUBODUNREGCAL_RANGE_SHIFT (3) |
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#define | EMU_BUBODUNREGCAL_RANGE_MASK (0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT) |
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#define | EMU_BUBODUNREGCAL_RANGE(v) |
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#define | EMU_BUBODUNREGCAL_THRES_SHIFT (0) |
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#define | EMU_BUBODUNREGCAL_THRES_MASK (0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT) |
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#define | EMU_BUBODUNREGCAL_THRES(v) |
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