libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
dwt.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_CM3_DWT_H
21#define LIBOPENCM3_CM3_DWT_H
22
23#include <libopencm3/cm3/common.h>
24#include <libopencm3/cm3/memorymap.h>
25
26/**
27 * @defgroup cm_dwt Cortex-M Data Watch and Trace unit.
28 * @ingroup CM3_defines
29 * System Control Space (SCS) => Data Watchpoint and Trace (DWT).
30 * See "ARMv7-M Architecture Reference Manual"
31 * and "ARMv6-M Architecture Reference Manual"
32 * The DWT is an optional debug unit that provides watchpoints, data tracing,
33 * and system profiling for the processor.
34 * @{
35 */
36
37/*****************************************************************************/
38/* Register definitions */
39/*****************************************************************************/
40
41/** DWT Control register
42 * Purpose Provides configuration and status information for the DWT block, and
43 * used to control features of the block
44 * Usage constraints: There are no usage constraints.
45 * Configurations Always implemented.
46 */
47#define DWT_CTRL MMIO32(DWT_BASE + 0x00)
48
49/* Those defined only on ARMv7 and above */
50#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
51
52/**
53 * DWT_CYCCNT register
54 * Cycle Count Register (Shows or sets the value of the processor cycle
55 * counter, CYCCNT)
56 * When enabled, CYCCNT increments on each processor clock cycle. On overflow,
57 * CYCCNT wraps to zero.
58 *
59 * Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
60 * Usage constraints: The DWT unit suspends CYCCNT counting when the processor
61 * is in Debug state.
62 * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
63 * register, DWT_CTRL.
64 * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
65 * register is UNK/SBZP.
66*/
67#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
68
69/** DWT_CPICNT register
70 * Purpose Counts additional cycles required to execute multi-cycle
71 * instructions and instruction fetch stalls.
72 * Usage constraints: The counter initializes to 0 when software enables its
73 * counter overflow event by
74 * setting the DWT_CTRL.CPIEVTENA bit to 1.
75 * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
76 * register, DWT_CTRL.
77 * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
78 * include the profiling counters, this register is UNK/SBZP.
79 */
80#define DWT_CPICNT MMIO32(DWT_BASE + 0x08)
81#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
82#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
83#define DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
84#define DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
85
86#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
87
88#define DWT_PCSR MMIO32(DWT_BASE + 0x1C)
89#define DWT_COMP(n) MMIO32(DWT_BASE + 0x20 + (n) * 16)
90#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16)
91#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16)
92
93/* CoreSight Lock Status Register for this peripheral */
94#define DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET)
95/* CoreSight Lock Access Register for this peripheral */
96#define DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET)
97
98
99/*****************************************************************************/
100/* Register values */
101/*****************************************************************************/
102
103/* --- DWT_CTRL values ---------------------------------------------------- */
104
105#define DWT_CTRL_NUMCOMP_SHIFT 28
106#define DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT)
107
108/* Those defined only on ARMv7 and above */
109#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
110
111#define DWT_CTRL_NOTRCPKT (1 << 27)
112#define DWT_CTRL_NOEXTTRIG (1 << 26)
113#define DWT_CTRL_NOCYCCNT (1 << 25)
114#define DWT_CTRL_NOPRFCCNT (1 << 24)
115
116#define DWT_CTRL_CYCEVTENA (1 << 22)
117#define DWT_CTRL_FOLDEVTENA (1 << 21)
118#define DWT_CTRL_LSUEVTENA (1 << 20)
119#define DWT_CTRL_SLEEPEVTENA (1 << 19)
120#define DWT_CTRL_EXCEVTENA (1 << 18)
121#define DWT_CTRL_CPIEVTENA (1 << 17)
122#define DWT_CTRL_EXCTRCENA (1 << 16)
123#define DWT_CTRL_PCSAMPLENA (1 << 12)
124
125#define DWT_CTRL_SYNCTAP_SHIFT 10
126#define DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT)
127#define DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT)
128#define DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT)
129#define DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT)
130#define DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT)
131
132#define DWT_CTRL_CYCTAP (1 << 9)
133
134#define DWT_CTRL_POSTCNT_SHIFT 5
135#define DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT)
136
137#define DWT_CTRL_POSTPRESET_SHIFT 1
138#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT)
139
140/**
141 * CYCCNTENA Enables the Cycle counter.
142 * 0 = Disabled, 1 = Enabled
143 * This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
144 */
145#define DWT_CTRL_CYCCNTENA (1 << 0)
146
147#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
148
149/* --- DWT_MASK(x) values -------------------------------------------------- */
150
151#define DWT_MASKx_MASK 0x0F
152
153/* --- DWT_FUNCTION(x) values ---------------------------------------------- */
154
155#define DWT_FUNCTIONx_MATCHED (1 << 24)
156
157/* Those defined only on ARMv7 and above */
158#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
159
160#define DWT_FUNCTIONx_DATAVADDR1_SHIFT 16
161#define DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT)
162
163#define DWT_FUNCTIONx_DATAVADDR0_SHIFT 12
164#define DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT)
165
166#define DWT_FUNCTIONx_DATAVSIZE_SHIFT 10
167#define DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
168#define DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
169#define DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
170#define DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
171
172#define DWT_FUNCTIONx_LNK1ENA (1 << 9)
173#define DWT_FUNCTIONx_DATAVMATCH (1 << 8)
174#define DWT_FUNCTIONx_CYCMATCH (1 << 7)
175#define DWT_FUNCTIONx_EMITRANGE (1 << 5)
176
177#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
178
179#define DWT_FUNCTIONx_FUNCTION 15
180#define DWT_FUNCTIONx_FUNCTION_DISABLED 0
181
182/* Those defined only on ARMv6 */
183#if defined(__ARM_ARCH_6M__)
184
185#define DWT_FUNCTIONx_FUNCTION_PCWATCH 4
186#define DWT_FUNCTIONx_FUNCTION_DWATCH_R 5
187#define DWT_FUNCTIONx_FUNCTION_DWATCH_W 6
188#define DWT_FUNCTIONx_FUNCTION_DWATCH_RW 7
189
190#endif /* defined(__ARM_ARCH_6M__)*/
191
192/*****************************************************************************/
193/* API definitions */
194/*****************************************************************************/
195
196/*****************************************************************************/
197/* API Functions */
198/*****************************************************************************/
199
200BEGIN_DECLS
201
202bool dwt_enable_cycle_counter(void);
203uint32_t dwt_read_cycle_counter(void);
204
205END_DECLS
206
207/**@}*/
208
209#endif /* LIBOPENCM3_CM3_DWT_H */
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
dwt_read_cycle_counter
uint32_t dwt_read_cycle_counter(void)
DebugTrace Read the CPU cycle counter.
Definition: dwt.c:90
dwt_enable_cycle_counter
bool dwt_enable_cycle_counter(void)
DebugTrace Enable the CPU cycle counter.
Definition: dwt.c:58