System Control Space (SCS) => Data Watchpoint and Trace (DWT). More...
Functions | |
| bool | dwt_enable_cycle_counter (void) |
| DebugTrace Enable the CPU cycle counter. More... | |
| uint32_t | dwt_read_cycle_counter (void) |
| DebugTrace Read the CPU cycle counter. More... | |
Detailed Description
System Control Space (SCS) => Data Watchpoint and Trace (DWT).
See "ARMv7-M Architecture Reference Manual" and "ARMv6-M Architecture Reference Manual" The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling for the processor.
Macro Definition Documentation
◆ DWT_COMP
◆ DWT_CPICNT
DWT_CPICNT register Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls.
Usage constraints: The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.CPIEVTENA bit to 1. Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL. If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK/SBZP.
◆ DWT_CTRL
◆ DWT_CTRL_CPIEVTENA
◆ DWT_CTRL_CYCCNTENA
| #define DWT_CTRL_CYCCNTENA (1 << 0) |
◆ DWT_CTRL_CYCEVTENA
◆ DWT_CTRL_CYCTAP
◆ DWT_CTRL_EXCEVTENA
◆ DWT_CTRL_EXCTRCENA
◆ DWT_CTRL_FOLDEVTENA
◆ DWT_CTRL_LSUEVTENA
◆ DWT_CTRL_NOCYCCNT
◆ DWT_CTRL_NOEXTTRIG
◆ DWT_CTRL_NOPRFCCNT
◆ DWT_CTRL_NOTRCPKT
◆ DWT_CTRL_NUMCOMP
| #define DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT) |
◆ DWT_CTRL_NUMCOMP_SHIFT
◆ DWT_CTRL_PCSAMPLENA
◆ DWT_CTRL_POSTCNT
| #define DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT) |
◆ DWT_CTRL_POSTCNT_SHIFT
◆ DWT_CTRL_POSTPRESET
| #define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT) |
◆ DWT_CTRL_POSTPRESET_SHIFT
◆ DWT_CTRL_SLEEPEVTENA
◆ DWT_CTRL_SYNCTAP
| #define DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT) |
◆ DWT_CTRL_SYNCTAP_BIT24
| #define DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT) |
◆ DWT_CTRL_SYNCTAP_BIT26
| #define DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT) |
◆ DWT_CTRL_SYNCTAP_BIT28
| #define DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT) |
◆ DWT_CTRL_SYNCTAP_DISABLED
| #define DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT) |
◆ DWT_CTRL_SYNCTAP_SHIFT
◆ DWT_CYCCNT
DWT_CYCCNT register Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) When enabled, CYCCNT increments on each processor clock cycle.
On overflow, CYCCNT wraps to zero.
Purpose Shows or sets the value of the processor cycle counter, CYCCNT. Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state. Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL. When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP.
◆ DWT_EXCCNT
◆ DWT_FOLDCNT
◆ DWT_FUNCTION
◆ DWT_FUNCTIONx_CYCMATCH
◆ DWT_FUNCTIONx_DATAVADDR0
| #define DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT) |
◆ DWT_FUNCTIONx_DATAVADDR0_SHIFT
◆ DWT_FUNCTIONx_DATAVADDR1
| #define DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT) |
◆ DWT_FUNCTIONx_DATAVADDR1_SHIFT
◆ DWT_FUNCTIONx_DATAVMATCH
◆ DWT_FUNCTIONx_DATAVSIZE
| #define DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
◆ DWT_FUNCTIONx_DATAVSIZE_BYTE
| #define DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
◆ DWT_FUNCTIONx_DATAVSIZE_HALF
| #define DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
◆ DWT_FUNCTIONx_DATAVSIZE_SHIFT
◆ DWT_FUNCTIONx_DATAVSIZE_WORD
| #define DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
◆ DWT_FUNCTIONx_EMITRANGE
◆ DWT_FUNCTIONx_FUNCTION
◆ DWT_FUNCTIONx_FUNCTION_DISABLED
◆ DWT_FUNCTIONx_LNK1ENA
◆ DWT_FUNCTIONx_MATCHED
◆ DWT_LAR
| #define DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET) |
◆ DWT_LSR
| #define DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET) |
◆ DWT_LSUCNT
◆ DWT_MASK
◆ DWT_MASKx_MASK
◆ DWT_PCSR
◆ DWT_SLEEPCNT
Function Documentation
◆ dwt_enable_cycle_counter()
| bool dwt_enable_cycle_counter | ( | void | ) |
DebugTrace Enable the CPU cycle counter.
This function will try to enable the CPU cycle counter that is intended for benchmarking performance of the code. If function fails, the cycle counter isn't available on this architecture.
- Returns
- true, if success
Definition at line 58 of file dwt.c.
References DWT_CTRL, DWT_CTRL_CYCCNTENA, DWT_CTRL_NOCYCCNT, DWT_CYCCNT, SCS_DEMCR, and SCS_DEMCR_TRCENA.
◆ dwt_read_cycle_counter()
| uint32_t dwt_read_cycle_counter | ( | void | ) |
DebugTrace Read the CPU cycle counter.
This function reads the core cycle counter if it is enabled. It is the fastest clock running on the system.
- Note
- The CPU cycle counter must be enabled by dwt_enable_cycle_counter
- Returns
- 0 if cycle counter is not supported or enabled, the cycle counter value otherwise.
Definition at line 90 of file dwt.c.
References DWT_CTRL, DWT_CTRL_CYCCNTENA, and DWT_CYCCNT.
