libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
gd32/f1x0/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2019 Iceonwy Zheng <icenowy@aosc.io>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_MEMORYMAP_H
21#define LIBOPENCM3_MEMORYMAP_H
22
23#include <libopencm3/cm3/memorymap.h>
24
25/* --- GD32 specific peripheral definitions ------------------------------- */
26
27/* Memory map for all buses */
28#define FLASH_BASE (0x08000000U)
29#define PERIPH_BASE (0x40000000U)
30#define INFO_BASE (0x1ffff000U)
31#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
32#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
33#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
34#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x8000000)
35
36/* Register boundary addresses */
37
38/* APB1 */
39#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
40#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
41#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
42#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
43/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
44#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
45#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
46#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
47/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
48#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
49/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
50#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
51#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
52#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
53
54#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
55#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)
56#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
57
58#define BACKUP_REGS_BASE (RTC_BASE + 0x50)
59#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
60#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
61#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800)
62/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */
63
64/* APB2 */
65#define SYSCFG_COMP_BASE (PERIPH_BASE_APB2 + 0x0000)
66#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
67
68#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
69
70#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
71#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
72
73#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
74
75#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)
76#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)
77#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)
78
79/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */
80
81/* AHB1 */
82
83#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x00000)
84
85#define RCC_BASE (PERIPH_BASE_AHB1 + 0x01000)
86
87#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x02000)
88#define CRC_BASE (PERIPH_BASE_AHB1 + 0x03000)
89#define TSC_BASE (PERIPH_BASE_AHB1 + 0x03000)
90
91
92/* AHB 2 */
93
94#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)
95#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)
96#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)
97#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)
98#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)
99
100/* Device Electronic Signature */
101#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
102#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7ac)
103/* Ignore the "reserved for future use" half of the first word */
104#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
105#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
106#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
107
108
109#endif