#include <libopencm3/cm3/memorymap.h>
Go to the source code of this file.
Macro Definition Documentation
◆ ADC1_BASE
| #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) |
Definition at line 68 of file gd32/f1x0/memorymap.h.
◆ BACKUP_REGS_BASE
| #define BACKUP_REGS_BASE (RTC_BASE + 0x50) |
Definition at line 58 of file gd32/f1x0/memorymap.h.
◆ CEC_BASE
| #define CEC_BASE (PERIPH_BASE_APB1 + 0x7800) |
Definition at line 61 of file gd32/f1x0/memorymap.h.
◆ CRC_BASE
| #define CRC_BASE (PERIPH_BASE_AHB1 + 0x03000) |
Definition at line 88 of file gd32/f1x0/memorymap.h.
◆ DAC_BASE
| #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) |
Definition at line 60 of file gd32/f1x0/memorymap.h.
◆ DESIG_FLASH_SIZE_BASE
| #define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) |
Definition at line 101 of file gd32/f1x0/memorymap.h.
◆ DESIG_UNIQUE_ID0
| #define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) |
Definition at line 104 of file gd32/f1x0/memorymap.h.
◆ DESIG_UNIQUE_ID1
| #define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) |
Definition at line 105 of file gd32/f1x0/memorymap.h.
◆ DESIG_UNIQUE_ID2
| #define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) |
Definition at line 106 of file gd32/f1x0/memorymap.h.
◆ DESIG_UNIQUE_ID_BASE
| #define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7ac) |
Definition at line 102 of file gd32/f1x0/memorymap.h.
◆ DMA1_BASE
| #define DMA1_BASE (PERIPH_BASE_AHB1 + 0x00000) |
Definition at line 83 of file gd32/f1x0/memorymap.h.
◆ EXTI_BASE
| #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) |
Definition at line 66 of file gd32/f1x0/memorymap.h.
◆ FLASH_BASE
| #define FLASH_BASE (0x08000000U) |
Definition at line 28 of file gd32/f1x0/memorymap.h.
◆ FLASH_MEM_INTERFACE_BASE
| #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x02000) |
Definition at line 87 of file gd32/f1x0/memorymap.h.
◆ GPIO_PORT_A_BASE
| #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) |
Definition at line 94 of file gd32/f1x0/memorymap.h.
◆ GPIO_PORT_B_BASE
| #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) |
Definition at line 95 of file gd32/f1x0/memorymap.h.
◆ GPIO_PORT_C_BASE
| #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) |
Definition at line 96 of file gd32/f1x0/memorymap.h.
◆ GPIO_PORT_D_BASE
| #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00) |
Definition at line 97 of file gd32/f1x0/memorymap.h.
◆ GPIO_PORT_F_BASE
| #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) |
Definition at line 98 of file gd32/f1x0/memorymap.h.
◆ I2C1_BASE
| #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) |
Definition at line 51 of file gd32/f1x0/memorymap.h.
◆ I2C2_BASE
| #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) |
Definition at line 52 of file gd32/f1x0/memorymap.h.
◆ INFO_BASE
| #define INFO_BASE (0x1ffff000U) |
Definition at line 30 of file gd32/f1x0/memorymap.h.
◆ IWDG_BASE
| #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) |
Definition at line 46 of file gd32/f1x0/memorymap.h.
◆ PERIPH_BASE
| #define PERIPH_BASE (0x40000000U) |
Definition at line 29 of file gd32/f1x0/memorymap.h.
◆ PERIPH_BASE_AHB1
| #define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) |
Definition at line 33 of file gd32/f1x0/memorymap.h.
◆ PERIPH_BASE_AHB2
| #define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x8000000) |
Definition at line 34 of file gd32/f1x0/memorymap.h.
◆ PERIPH_BASE_APB1
| #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) |
Definition at line 31 of file gd32/f1x0/memorymap.h.
◆ PERIPH_BASE_APB2
| #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) |
Definition at line 32 of file gd32/f1x0/memorymap.h.
◆ POWER_CONTROL_BASE
| #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) |
Definition at line 59 of file gd32/f1x0/memorymap.h.
◆ RCC_BASE
| #define RCC_BASE (PERIPH_BASE_AHB1 + 0x01000) |
Definition at line 85 of file gd32/f1x0/memorymap.h.
◆ RTC_BASE
| #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) |
Definition at line 44 of file gd32/f1x0/memorymap.h.
◆ SPI1_BASE
| #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) |
Definition at line 71 of file gd32/f1x0/memorymap.h.
◆ SPI2_BASE
| #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) |
Definition at line 48 of file gd32/f1x0/memorymap.h.
◆ SYSCFG_COMP_BASE
| #define SYSCFG_COMP_BASE (PERIPH_BASE_APB2 + 0x0000) |
Definition at line 65 of file gd32/f1x0/memorymap.h.
◆ TIM14_BASE
| #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) |
Definition at line 42 of file gd32/f1x0/memorymap.h.
◆ TIM15_BASE
| #define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) |
Definition at line 75 of file gd32/f1x0/memorymap.h.
◆ TIM16_BASE
| #define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) |
Definition at line 76 of file gd32/f1x0/memorymap.h.
◆ TIM17_BASE
| #define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) |
Definition at line 77 of file gd32/f1x0/memorymap.h.
◆ TIM1_BASE
| #define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) |
Definition at line 70 of file gd32/f1x0/memorymap.h.
◆ TIM2_BASE
| #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) |
Definition at line 39 of file gd32/f1x0/memorymap.h.
◆ TIM3_BASE
| #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) |
Definition at line 40 of file gd32/f1x0/memorymap.h.
◆ TIM6_BASE
| #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) |
Definition at line 41 of file gd32/f1x0/memorymap.h.
◆ TSC_BASE
| #define TSC_BASE (PERIPH_BASE_AHB1 + 0x03000) |
Definition at line 89 of file gd32/f1x0/memorymap.h.
◆ USART1_BASE
| #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) |
Definition at line 73 of file gd32/f1x0/memorymap.h.
◆ USART2_BASE
| #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) |
Definition at line 50 of file gd32/f1x0/memorymap.h.
◆ USB_DEV_FS_BASE
| #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) |
Definition at line 54 of file gd32/f1x0/memorymap.h.
◆ USB_PMA_BASE
| #define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) |
Definition at line 55 of file gd32/f1x0/memorymap.h.
◆ USB_SRAM_BASE
| #define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) |
Definition at line 56 of file gd32/f1x0/memorymap.h.
◆ WWDG_BASE
| #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) |
Definition at line 45 of file gd32/f1x0/memorymap.h.
