The System Control Block is a section of the System Control Space.
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The System Control Block is a section of the System Control Space.
Other members of the SCS are, for instance, DWT, ITM, SYSTICKK. The exact details of the SCB are defined in the "Architecture Reference
Manual" for either ARMv7-M or ARMV6-m.
◆ SCB_CFSR_BFARVALID
#define SCB_CFSR_BFARVALID (1 << 15) |
◆ SCB_CFSR_DACCVIOL
#define SCB_CFSR_DACCVIOL (1 << 1) |
◆ SCB_CFSR_DIVBYZERO
#define SCB_CFSR_DIVBYZERO (1 << 25) |
◆ SCB_CFSR_IACCVIOL
#define SCB_CFSR_IACCVIOL (1 << 0) |
◆ SCB_CFSR_IBUSERR
#define SCB_CFSR_IBUSERR (1 << 8) |
◆ SCB_CFSR_IMPRECISERR
#define SCB_CFSR_IMPRECISERR (1 << 10) |
◆ SCB_CFSR_INVPC
#define SCB_CFSR_INVPC (1 << 18) |
◆ SCB_CFSR_INVSTATE
#define SCB_CFSR_INVSTATE (1 << 17) |
◆ SCB_CFSR_MMARVALID
#define SCB_CFSR_MMARVALID (1 << 7) |
◆ SCB_CFSR_MSTKERR
#define SCB_CFSR_MSTKERR (1 << 4) |
◆ SCB_CFSR_MUNSTKERR
#define SCB_CFSR_MUNSTKERR (1 << 3) |
◆ SCB_CFSR_NOCP
#define SCB_CFSR_NOCP (1 << 19) |
◆ SCB_CFSR_PRECISERR
#define SCB_CFSR_PRECISERR (1 << 9) |
◆ SCB_CFSR_STKERR
#define SCB_CFSR_STKERR (1 << 12) |
◆ SCB_CFSR_UNALIGNED
#define SCB_CFSR_UNALIGNED (1 << 24) |
◆ SCB_CFSR_UNDEFINSTR
#define SCB_CFSR_UNDEFINSTR (1 << 16) |
◆ SCB_CFSR_UNSTKERR
#define SCB_CFSR_UNSTKERR (1 << 11) |
◆ SCB_CPACR_CP10
#define SCB_CPACR_CP10 (1 << 20) |
◆ SCB_CPACR_CP11
#define SCB_CPACR_CP11 (1 << 22) |
◆ SCB_CPACR_FULL
#define SCB_CPACR_FULL 3 /* Full access */ |
◆ SCB_CPACR_NONE
#define SCB_CPACR_NONE 0 /* Access denied */ |
◆ SCB_CPACR_PRIV
#define SCB_CPACR_PRIV 1 /* Privileged access only */ |
◆ SCB_GET_EXCEPTION_STACK_FRAME
#define SCB_GET_EXCEPTION_STACK_FRAME |
( |
|
f | ) |
|
Value: do { \
__asm__ volatile ("mov %[frameptr], sp" \
: [frameptr]"=r" (f)); \
} while (0)
Definition at line 550 of file scb.h.
◆ SCB_HFSR_DEBUG_VT
#define SCB_HFSR_DEBUG_VT (1 << 31) |
◆ SCB_HFSR_FORCED
#define SCB_HFSR_FORCED (1 << 30) |
◆ SCB_HFSR_VECTTBL
#define SCB_HFSR_VECTTBL (1 << 1) |
◆ SCB_SHCSR_BUSFAULTACT
#define SCB_SHCSR_BUSFAULTACT (1 << 1) |
◆ SCB_SHCSR_BUSFAULTENA
#define SCB_SHCSR_BUSFAULTENA (1 << 17) |
◆ SCB_SHCSR_BUSFAULTPENDED
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) |
◆ SCB_SHCSR_MEMFAULTACT
#define SCB_SHCSR_MEMFAULTACT (1 << 0) |
◆ SCB_SHCSR_MEMFAULTENA
#define SCB_SHCSR_MEMFAULTENA (1 << 16) |
◆ SCB_SHCSR_MEMFAULTPENDED
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) |
◆ SCB_SHCSR_MONITORACT
#define SCB_SHCSR_MONITORACT (1 << 8) |
◆ SCB_SHCSR_PENDSVACT
#define SCB_SHCSR_PENDSVACT (1 << 10) |
◆ SCB_SHCSR_SVCALLACT
#define SCB_SHCSR_SVCALLACT (1 << 7) |
◆ SCB_SHCSR_SVCALLPENDED
#define SCB_SHCSR_SVCALLPENDED (1 << 15) |
◆ SCB_SHCSR_SYSTICKACT
#define SCB_SHCSR_SYSTICKACT (1 << 11) |
◆ SCB_SHCSR_USGFAULTACT
#define SCB_SHCSR_USGFAULTACT (1 << 3) |
◆ SCB_SHCSR_USGFAULTENA
#define SCB_SHCSR_USGFAULTENA (1 << 18) |
◆ SCB_SHCSR_USGFAULTPENDED
#define SCB_SHCSR_USGFAULTPENDED (1 << 12) |
◆ SCB_SHPR_PRI_10_RESERVED
#define SCB_SHPR_PRI_10_RESERVED 6 |
◆ SCB_SHPR_PRI_11_SVCALL
#define SCB_SHPR_PRI_11_SVCALL 7 |
◆ SCB_SHPR_PRI_12_RESERVED
#define SCB_SHPR_PRI_12_RESERVED 8 |
◆ SCB_SHPR_PRI_13_RESERVED
#define SCB_SHPR_PRI_13_RESERVED 9 |
◆ SCB_SHPR_PRI_14_PENDSV
#define SCB_SHPR_PRI_14_PENDSV 10 |
◆ SCB_SHPR_PRI_15_SYSTICK
#define SCB_SHPR_PRI_15_SYSTICK 11 |
◆ SCB_SHPR_PRI_4_MEMMANAGE
#define SCB_SHPR_PRI_4_MEMMANAGE 0 |
◆ SCB_SHPR_PRI_5_BUSFAULT
#define SCB_SHPR_PRI_5_BUSFAULT 1 |
◆ SCB_SHPR_PRI_6_USAGEFAULT
#define SCB_SHPR_PRI_6_USAGEFAULT 2 |
◆ SCB_SHPR_PRI_7_RESERVED
#define SCB_SHPR_PRI_7_RESERVED 3 |
◆ SCB_SHPR_PRI_8_RESERVED
#define SCB_SHPR_PRI_8_RESERVED 4 |
◆ SCB_SHPR_PRI_9_RESERVED
#define SCB_SHPR_PRI_9_RESERVED 5 |
◆ scb_reset_core()
void scb_reset_core |
( |
void |
| ) |
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◆ scb_reset_system()
void scb_reset_system |
( |
void |
| ) |
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◆ scb_set_priority_grouping()
void scb_set_priority_grouping |
( |
uint32_t |
prigroup | ) |
|