libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
timer.h
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1/** @defgroup timer_defines General Purpose Timers
2 *
3 * @brief <b>Defined Constants and Types for the LM4F General Purpose Timers</b>
4 *
5 * @ingroup LM4Fxx_defines
6 *
7 * @version 1.0.0
8 *
9 * LGPL License Terms @ref lgpl_license
10 */
11
12/*
13 * This file is part of the libopencm3 project.
14 *
15 * Copyright 2018 Karl Palsson <karlp@tweak.net.au>
16 *
17 * This library is free software: you can redistribute it and/or modify
18 * it under the terms of the GNU Lesser General Public License as published by
19 * the Free Software Foundation, either version 3 of the License, or
20 * (at your option) any later version.
21 *
22 * This library is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU Lesser General Public License for more details.
26 *
27 * You should have received a copy of the GNU Lesser General Public License
28 * along with this library. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31#pragma once
32
33#include <libopencm3/cm3/common.h>
34#include <libopencm3/lm4f/memorymap.h>
35
36/**@{*/
37
38/** @defgroup timer_registers GP Timer registers
39 * Unless otherwise specified, these registers are RW
40 *@{*/
41
42/** Configuration */
43#define GPTMCFG(tim_base) MMIO32((tim_base) + 0)
44/** Timer A mode */
45#define GPTMTAMR(tim_base) MMIO32((tim_base) + 0x4)
46/** Timer B mode */
47#define GPTMTBMR(tim_base) MMIO32((tim_base) + 0x8)
48/** Control */
49#define GPTMCTL(tim_base) MMIO32((tim_base) + 0xc)
50/** Synchronize */
51#define GPTMSYNC(tim_base) MMIO32((tim_base) + 0x10)
52/** Interrupt mask */
53#define GPTMIMR(tim_base) MMIO32((tim_base) + 0x18)
54/** Raw interrupt status (RO) */
55#define GPTMRIS(tim_base) MMIO32((tim_base) + 0x1c)
56/** Masked interrupt status (RO) */
57#define GPTMMIS(tim_base) MMIO32((tim_base) + 0x20)
58/** Interrupt clear (W1C) */
59#define GPTMICR(tim_base) MMIO32((tim_base) + 0x24)
60/** Timer A Interval load */
61#define GPTMTAILR(tim_base) MMIO32((tim_base) + 0x28)
62/** Timer B Interval load */
63#define GPTMTBILR(tim_base) MMIO32((tim_base) + 0x2c)
64/** Timer A match */
65#define GPTMTAMATCHR(tim_base) MMIO32((tim_base) + 0x30)
66/** Timer B match */
67#define GPTMTBMATCHR(tim_base) MMIO32((tim_base) + 0x34)
68/** Timer A prescale */
69#define GPTMTAPR(tim_base) MMIO32((tim_base) + 0x38)
70/** Timer B prescale */
71#define GPTMTBPR(tim_base) MMIO32((tim_base) + 0x3c)
72/** Timer A prescale match */
73#define GPTMTAPMR(tim_base) MMIO32((tim_base) + 0x40)
74/** Timer A prescale match */
75#define GPTMTBPMR(tim_base) MMIO32((tim_base) + 0x44)
76/* Timer A (RO) */
77#define GPTMTAR(tim_base) MMIO32((tim_base) + 0x48)
78/* Timer B (RO) */
79#define GPTMTBR(tim_base) MMIO32((tim_base) + 0x4c)
80/* Timer A value */
81#define GPTMTAV(tim_base) MMIO32((tim_base) + 0x50)
82/* Timer B value */
83#define GPTMTBV(tim_base) MMIO32((tim_base) + 0x54)
84/** RTC Predivide (RO) */
85#define GPTMRTCPD(tim_base) MMIO32((tim_base) + 0x58)
86/** Timer A prescale snapshot (RO) */
87#define GPTMTAPS(tim_base) MMIO32((tim_base) + 0x5c)
88/** Timer B prescale snapshot (RO) */
89#define GPTMTBPS(tim_base) MMIO32((tim_base) + 0x60)
90/** Timer A prescale value (RO) */
91#define GPTMTAPV(tim_base) MMIO32((tim_base) + 0x64)
92/** Timer B prescale value (RO) */
93#define GPTMTBPV(tim_base) MMIO32((tim_base) + 0x68)
94/** Peripheral properties (RO) */
95#define GPTMPP(tim_base) MMIO32((tim_base) + 0xfc0)
96
97/**@}*/
98
99/**@}*/