libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
|
Unless otherwise specified, these registers are RW. More...
Macros | |
#define | GPTMCFG(tim_base) MMIO32((tim_base) + 0) |
Configuration. More... | |
#define | GPTMTAMR(tim_base) MMIO32((tim_base) + 0x4) |
Timer A mode. More... | |
#define | GPTMTBMR(tim_base) MMIO32((tim_base) + 0x8) |
Timer B mode. More... | |
#define | GPTMCTL(tim_base) MMIO32((tim_base) + 0xc) |
Control. More... | |
#define | GPTMSYNC(tim_base) MMIO32((tim_base) + 0x10) |
Synchronize. More... | |
#define | GPTMIMR(tim_base) MMIO32((tim_base) + 0x18) |
Interrupt mask. More... | |
#define | GPTMRIS(tim_base) MMIO32((tim_base) + 0x1c) |
Raw interrupt status (RO) More... | |
#define | GPTMMIS(tim_base) MMIO32((tim_base) + 0x20) |
Masked interrupt status (RO) More... | |
#define | GPTMICR(tim_base) MMIO32((tim_base) + 0x24) |
Interrupt clear (W1C) More... | |
#define | GPTMTAILR(tim_base) MMIO32((tim_base) + 0x28) |
Timer A Interval load. More... | |
#define | GPTMTBILR(tim_base) MMIO32((tim_base) + 0x2c) |
Timer B Interval load. More... | |
#define | GPTMTAMATCHR(tim_base) MMIO32((tim_base) + 0x30) |
Timer A match. More... | |
#define | GPTMTBMATCHR(tim_base) MMIO32((tim_base) + 0x34) |
Timer B match. More... | |
#define | GPTMTAPR(tim_base) MMIO32((tim_base) + 0x38) |
Timer A prescale. More... | |
#define | GPTMTBPR(tim_base) MMIO32((tim_base) + 0x3c) |
Timer B prescale. More... | |
#define | GPTMTAPMR(tim_base) MMIO32((tim_base) + 0x40) |
Timer A prescale match. More... | |
#define | GPTMTBPMR(tim_base) MMIO32((tim_base) + 0x44) |
Timer A prescale match. More... | |
#define | GPTMTAR(tim_base) MMIO32((tim_base) + 0x48) |
#define | GPTMTBR(tim_base) MMIO32((tim_base) + 0x4c) |
#define | GPTMTAV(tim_base) MMIO32((tim_base) + 0x50) |
#define | GPTMTBV(tim_base) MMIO32((tim_base) + 0x54) |
#define | GPTMRTCPD(tim_base) MMIO32((tim_base) + 0x58) |
RTC Predivide (RO) More... | |
#define | GPTMTAPS(tim_base) MMIO32((tim_base) + 0x5c) |
Timer A prescale snapshot (RO) More... | |
#define | GPTMTBPS(tim_base) MMIO32((tim_base) + 0x60) |
Timer B prescale snapshot (RO) More... | |
#define | GPTMTAPV(tim_base) MMIO32((tim_base) + 0x64) |
Timer A prescale value (RO) More... | |
#define | GPTMTBPV(tim_base) MMIO32((tim_base) + 0x68) |
Timer B prescale value (RO) More... | |
#define | GPTMPP(tim_base) MMIO32((tim_base) + 0xfc0) |
Peripheral properties (RO) More... | |
Unless otherwise specified, these registers are RW.
#define GPTMCFG | ( | tim_base | ) | MMIO32((tim_base) + 0) |
#define GPTMCTL | ( | tim_base | ) | MMIO32((tim_base) + 0xc) |
#define GPTMICR | ( | tim_base | ) | MMIO32((tim_base) + 0x24) |
#define GPTMIMR | ( | tim_base | ) | MMIO32((tim_base) + 0x18) |
#define GPTMMIS | ( | tim_base | ) | MMIO32((tim_base) + 0x20) |
#define GPTMPP | ( | tim_base | ) | MMIO32((tim_base) + 0xfc0) |
#define GPTMRIS | ( | tim_base | ) | MMIO32((tim_base) + 0x1c) |
#define GPTMRTCPD | ( | tim_base | ) | MMIO32((tim_base) + 0x58) |
#define GPTMSYNC | ( | tim_base | ) | MMIO32((tim_base) + 0x10) |
#define GPTMTAILR | ( | tim_base | ) | MMIO32((tim_base) + 0x28) |
#define GPTMTAMATCHR | ( | tim_base | ) | MMIO32((tim_base) + 0x30) |
#define GPTMTAMR | ( | tim_base | ) | MMIO32((tim_base) + 0x4) |
#define GPTMTAPMR | ( | tim_base | ) | MMIO32((tim_base) + 0x40) |
#define GPTMTAPR | ( | tim_base | ) | MMIO32((tim_base) + 0x38) |
#define GPTMTAPS | ( | tim_base | ) | MMIO32((tim_base) + 0x5c) |
#define GPTMTAPV | ( | tim_base | ) | MMIO32((tim_base) + 0x64) |
#define GPTMTBILR | ( | tim_base | ) | MMIO32((tim_base) + 0x2c) |
#define GPTMTBMATCHR | ( | tim_base | ) | MMIO32((tim_base) + 0x34) |
#define GPTMTBMR | ( | tim_base | ) | MMIO32((tim_base) + 0x8) |
#define GPTMTBPMR | ( | tim_base | ) | MMIO32((tim_base) + 0x44) |
#define GPTMTBPR | ( | tim_base | ) | MMIO32((tim_base) + 0x3c) |
#define GPTMTBPS | ( | tim_base | ) | MMIO32((tim_base) + 0x60) |
#define GPTMTBPV | ( | tim_base | ) | MMIO32((tim_base) + 0x68) |