libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
lpc17xx/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2012 Silvio Gissi <silvio.gissi@outlook.com>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef LPC17XX_MEMORYMAP_H
22#define LPC17XX_MEMORYMAP_H
23
24#include <libopencm3/cm3/memorymap.h>
25
26/* --- LPC17XX specific peripheral definitions ----------------------------- */
27
28/* Memory map for all busses */
29#define PERIPH_BASE_GPIO (0x2009C000U)
30#define PERIPH_BASE_APB0 (0x40000000U)
31#define PERIPH_BASE_APB1 (0x40080000U)
32#define PERIPH_BASE_AHB (0x50000000U)
33
34/* Register boundary addresses */
35
36/* GPIO */
37#define GPIO_PIO0_BASE (PERIPH_BASE_GPIO + 0x00)
38#define GPIO_PIO1_BASE (PERIPH_BASE_GPIO + 0x20)
39#define GPIO_PIO2_BASE (PERIPH_BASE_GPIO + 0x40)
40#define GPIO_PIO3_BASE (PERIPH_BASE_GPIO + 0x60)
41#define GPIO_PIO4_BASE (PERIPH_BASE_GPIO + 0x80)
42
43/* APB0 */
44#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
45#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
46#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
47#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
48#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
49/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
50#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
51#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
52#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
53#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
54#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
55#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
56#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
57#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
58#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
59#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
60#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
61#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
62#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
63/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
64#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
65/* PERIPH_BASE_APB0 + 0X60000 (0x4006 0000 - 0x4007 BFFF): Reserved */
66
67/* APB1 */
68/* PERIPH_BASE_APB1 + 0X00000 (0x4008 0000 - 0x4008 7FFF): Reserved */
69#define SSP0_BASE (PERIPH_BASE_APB1 + 0x08000)
70#define DAC_BASE (PERIPH_BASE_APB1 + 0x0c000)
71#define TIMER2_BASE (PERIPH_BASE_APB1 + 0x10000)
72#define TIMER3_BASE (PERIPH_BASE_APB1 + 0x14000)
73#define UART2_BASE (PERIPH_BASE_APB1 + 0x18000)
74#define UART3_BASE (PERIPH_BASE_APB1 + 0x1c000)
75#define I2C2_BASE (PERIPH_BASE_APB1 + 0x20000)
76/* PERIPH_BASE_APB1 + 0X24000 (0x400A 4000 - 0x400A 7FFF): Reserved */
77#define I2S_BASE (PERIPH_BASE_APB1 + 0x28000)
78/* PERIPH_BASE_APB1 + 0X2C000 (0x400A C000 - 0x400A FFFF): Reserved */
79#define RIT_BASE (PERIPH_BASE_APB1 + 0x30000)
80/* PERIPH_BASE_APB1 + 0X34000 (0x400B 4000 - 0x400B 7FFF): Reserved */
81#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x38000)
82#define QEI_BASE (PERIPH_BASE_APB1 + 0x3c000)
83/* PERIPH_BASE_APB1 + 0X40000 (0x400C 0000 - 0x400F BFFF): Reserved */
84#define SYSCON_BASE (PERIPH_BASE_APB1 + 0x7c000)
85
86/* AHB */
87#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x00000)
88#define GPDMA_BASE (PERIPH_BASE_AHB + 0x04000)
89/* PERIPH_BASE_AHB + 0X08000 (0x5000 8000 - 0x5000 BFFF): Reserved */
90#define USB_BASE (PERIPH_BASE_AHB + 0x0c000)
91/* PERIPH_BASE_AHB + 0X10000 (0x5001 0000 - 0x501F FFFF): Reserved */
92
93#endif