libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
i2s.h
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1/** @defgroup i2s_defines I2S Defines
2
3@brief <b>Defined Constants and Types for the LPC43xx I2S</b>
4
5@ingroup LPC43xx_defines
6
7@version 1.0.0
8
9@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
10
11@date 10 March 2013
12
13LGPL License Terms @ref lgpl_license
14 */
15/*
16 * This file is part of the libopencm3 project.
17 *
18 * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34#ifndef LPC43XX_I2S_H
35#define LPC43XX_I2S_H
36
37/**@{*/
38
39#include <libopencm3/cm3/common.h>
40#include <libopencm3/lpc43xx/memorymap.h>
41
42/* --- Convenience macros -------------------------------------------------- */
43
44/* I2S port base addresses (for convenience) */
45#define I2S0 I2S0_BASE
46#define I2S1 I2S1_BASE
47
48/* --- I2S registers ------------------------------------------------------- */
49
50/* I2S Digital Audio Output Register */
51#define I2S_DAO(port) MMIO32((port) + 0x000)
52#define I2S0_DAO I2S_DAO(I2S0)
53#define I2S1_DAO I2S_DAO(I2S1)
54
55/* I2S Digital Audio Input Register */
56#define I2S_DAI(port) MMIO32((port) + 0x004)
57#define I2S0_DAI I2S_DAI(I2S0)
58#define I2S1_DAI I2S_DAI(I2S1)
59
60/* I2S Transmit FIFO */
61#define I2S_TXFIFO(port) MMIO32((port) + 0x008)
62#define I2S0_TXFIFO I2S_TXFIFO(I2S0)
63#define I2S1_TXFIFO I2S_TXFIFO(I2S1)
64
65/* I2S Receive FIFO */
66#define I2S_RXFIFO(port) MMIO32((port) + 0x00C)
67#define I2S0_RXFIFO I2S_RXFIFO(I2S0)
68#define I2S1_RXFIFO I2S_RXFIFO(I2S1)
69
70/* I2S Status Feedback Register */
71#define I2S_STATE(port) MMIO32((port) + 0x010)
72#define I2S0_STATE I2S_STATE(I2S0)
73#define I2S1_STATE I2S_STATE(I2S1)
74
75/* I2S DMA Configuration Register 1 */
76#define I2S_DMA1(port) MMIO32((port) + 0x014)
77#define I2S0_DMA1 I2S_DMA1(I2S0)
78#define I2S1_DMA1 I2S_DMA1(I2S1)
79
80/* I2S DMA Configuration Register 2 */
81#define I2S_DMA2(port) MMIO32((port) + 0x018)
82#define I2S0_DMA2 I2S_DMA2(I2S0)
83#define I2S1_DMA2 I2S_DMA2(I2S1)
84
85/* I2S Interrupt Request Control Register */
86#define I2S_IRQ(port) MMIO32((port) + 0x01C)
87#define I2S0_IRQ I2S_IRQ(I2S0)
88#define I2S1_IRQ I2S_IRQ(I2S1)
89
90/* I2S Transmit MCLK divider */
91#define I2S_TXRATE(port) MMIO32((port) + 0x020)
92#define I2S0_TXRATE I2S_TXRATE(I2S0)
93#define I2S1_TXRATE I2S_TXRATE(I2S1)
94
95/* I2S Receive MCLK divider */
96#define I2S_RXRATE(port) MMIO32((port) + 0x024)
97#define I2S0_RXRATE I2S_RXRATE(I2S0)
98#define I2S1_RXRATE I2S_RXRATE(I2S1)
99
100/* I2S Transmit bit rate divider */
101#define I2S_TXBITRATE(port) MMIO32((port) + 0x028)
102#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0)
103#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1)
104
105/* I2S Receive bit rate divider */
106#define I2S_RXBITRATE(port) MMIO32((port) + 0x02C)
107#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0)
108#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1)
109
110/* I2S Transmit mode control */
111#define I2S_TXMODE(port) MMIO32((port) + 0x030)
112#define I2S0_TXMODE I2S_TXMODE(I2S0)
113#define I2S1_TXMODE I2S_TXMODE(I2S1)
114
115/* I2S Receive mode control */
116#define I2S_RXMODE(port) MMIO32((port) + 0x034)
117#define I2S0_RXMODE I2S_RXMODE(I2S0)
118#define I2S1_RXMODE I2S_RXMODE(I2S1)
119
120/**@}*/
121
122#endif