libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
lpc43xx/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef LPC43XX_MEMORYMAP_H
22#define LPC43XX_MEMORYMAP_H
23
24#include <libopencm3/cm3/common.h>
25
26/* --- LPC43XX specific peripheral definitions ----------------------------- */
27
28/* Memory map for all busses */
29#define PERIPH_BASE_AHB (0x40000000U)
30#define PERIPH_BASE_APB0 (0x40080000U)
31#define PERIPH_BASE_APB1 (0x400A0000U)
32#define PERIPH_BASE_APB2 (0x400C0000U)
33#define PERIPH_BASE_APB3 (0x400E0000U)
34
35/* Register boundary addresses */
36
37/* AHB (0x4000 0000 - 0x4001 2000) */
38#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
39/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
40#define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)
41#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)
42#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000)
43#define EMC_BASE (PERIPH_BASE_AHB + 0x05000)
44#define USB0_BASE (PERIPH_BASE_AHB + 0x06000)
45#define USB1_BASE (PERIPH_BASE_AHB + 0x07000)
46#define LCD_BASE (PERIPH_BASE_AHB + 0x08000)
47/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
48#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
49
50/* 0x4001 2000 - 0x4003 FFFF Reserved */
51
52/* RTC domain peripherals */
53#define ATIMER_BASE (0x40040000U)
54#define BACKUP_REG_BASE (0x40041000U)
55#define PMC_BASE (0x40042000U)
56#define CREG_BASE (0x40043000U)
57#define EVENTROUTER_BASE (0x40044000U)
58#define OTP_BASE (0x40045000U)
59#define RTC_BASE (0x40046000U)
60/* 0x4004 7000 - 0x4004 FFFF Reserved */
61
62/* clocking/reset control peripherals */
63#define CGU_BASE (0x40050000U)
64#define CCU1_BASE (0x40051000U)
65#define CCU2_BASE (0x40052000U)
66#define RGU_BASE (0x40053000U)
67/* 0x4005 4000 - 0x4005 FFFF Reserved */
68
69/* 0x4006 0000 - 0x4007 FFFF Reserved */
70
71/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
72#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
73#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
74#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
75#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)
76#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
77#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)
78#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000)
79#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
80#define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
81#define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
82/* 0x4008 A000 - 0x4008 FFFF Reserved */
83
84/* 0x4009 0000 - 0x4009 FFFF Reserved */
85
86/* APB1 (0x400A 0000 - 0x400A FFFF) */
87#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)
88#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)
89#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)
90#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)
91#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)
92/* 0x400A 5000 - 0x400A FFFF Reserved */
93
94/* 0x400B 0000 - 0x400B FFFF Reserved */
95
96/* APB2 (0x400C 0000 - 0x400C FFFF) */
97#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)
98#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000)
99#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000)
100#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)
101#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)
102#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)
103#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000)
104#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)
105/* 0x400C 8000 - 0x400C FFFF Reserved */
106
107/* 0x400D 0000 - 0x400D FFFF Reserved */
108
109/* APB3 (0x400E 0000 - 0x400E FFFF) */
110#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)
111#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000)
112#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)
113#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000)
114#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)
115/* 0x400E 5000 - 0x400E FFFF Reserved */
116
117/* 0x400F 0000 - 0x400F 0FFF Reserved */
118
119#define AES_BASE (0x400F1000U)
120
121/* 0x400F 2000 - 0x400F 3FFF Reserved */
122
123#define GPIO_PORT_BASE (0x400F4000U)
124
125/* 0x400F 8000 - 0x400F FFFF Reserved */
126
127#define SPI_PORT_BASE (0x40100000U)
128#define SGPIO_PORT_BASE (0x40101000U)
129
130/* 0x4010 2000 - 0x41FF FFFF Reserved */
131
132/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
133
134/* 0x4400 0000 - 0x5FFF FFFF Reserved */
135
136/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
137
138#endif