libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
common/gpio.h
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1/** @addtogroup gpio_defines
2 *
3 * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
4 * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
5 *
6 **/
7
8/*
9 * This file is part of the libopencm3 project.
10 *
11 * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
12 * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
13 *
14 * This library is free software: you can redistribute it and/or modify
15 * it under the terms of the GNU Lesser General Public License as published by
16 * the Free Software Foundation, either version 3 of the License, or
17 * (at your option) any later version.
18 *
19 * This library is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU Lesser General Public License for more details.
23 *
24 * You should have received a copy of the GNU Lesser General Public License
25 * along with this library. If not, see <http://www.gnu.org/licenses/>.
26 */
27
28#pragma once
29
32/**@{*/
33
34/** @addtogroup gpio_port_id GPIO ports
35 * @{
36 */
37/** GPIO port */
38#define GPIO (GPIO_BASE)
39
40/**@}*/
41
42#define GPIO_OUT MMIO32(GPIO_BASE + 0x504)
43#define GPIO_OUTSET MMIO32(GPIO_BASE + 0x508)
44#define GPIO_OUTCLR MMIO32(GPIO_BASE + 0x50C)
45
46#define GPIO_IN MMIO32(GPIO_BASE + 0x510)
47
48#define GPIO_DIR MMIO32(GPIO_BASE + 0x514)
49#define GPIO_DIRSET MMIO32(GPIO_BASE + 0x518)
50#define GPIO_DIRCLR MMIO32(GPIO_BASE + 0x51C)
51
52#define GPIO_PIN_CNF(N) MMIO32(GPIO_BASE + 0x700 + 0x4 * (N))
53
54
55/* Pin mode (CPIO_CNF[1:0] - combines direction and analog/digital */
56
57#define GPIO_CNF_MODE_MASK 2
58#define GPIO_CNF_MODE_SHIFT 0
59
60/* Pin mode (MODE[1:0]) values */
61/** @defgroup gpio_mode GPIO Pin Mode
62@ingroup gpio_defines
63@{*/
64#define GPIO_MODE_INPUT 0
65#define GPIO_MODE_OUTPUT 1
66#define GPIO_MODE_ANALOG 2
67/**@}*/
68
69#define GPIO_CNF_PUPD_MASK 2
70#define GPIO_CNF_PUPD_SHIFT 2
71
72/** @defgroup gpio_pupd GPIO Output Pin Pullup
73@ingroup gpio_defines
74@{*/
75#define GPIO_PUPD_NONE 0x0
76#define GPIO_PUPD_PULLDOWN 0x1
77#define GPIO_PUPD_PULLUP 0x2
78/**@}*/
79
80#define GPIO_CNF_DRIVE_SHIFT 8
81#define GPIO_CNF_DRIVE_MASK 7
82
83/** @addtogroup gpio_drive GPIO drive configuration
84 * @{ */
85
86/** Standard 0, standard 1 */
87#define GPIO_CNF_DRIVE_S0S1 0
88
89/** High drive 0, standard 1 */
90#define GPIO_CNF_DRIVE_H0S1 1
91
92/** Standard 0, high drive 1 */
93#define GPIO_CNF_DRIVE_S0H1 2
94
95/** High drive 0, high drive 1 */
96#define GPIO_CNF_DRIVE_H0H1 3
97
98/** Disconnect 0, standard 1 (wired-or connections) */
99#define GPIO_CNF_DRIVE_D0S1 4
100
101/** Disconnect 0, high drive 1 (wired-or connections) */
102#define GPIO_CNF_DRIVE_D0H1 5
103
104/** Standard 0, disconnect 1 (wired-and connections) */
105#define GPIO_CNF_DRIVE_S0D1 6
106
107/** High drive 0, disconnect 1 (wired-and connections) */
108#define GPIO_CNF_DRIVE_H0D1 7
109
110/**@}*/
111
112#define GPIO_CNF_SENSE_SHIFT 16
113#define GPIO_CNF_SENSE_MASK 3
114
115/** @addtogroup gpio_sense GPIO sensing mechanism
116 * @{ */
117
118/** Pin sensing is disabled */
119#define GPIO_CNF_SENSE_DISABLE 0
120
121/** Pin sensing is active for high level */
122#define GPIO_CNF_SENSE_HIGH 2
123
124/** Pin sensing is active for low level */
125#define GPIO_CNF_SENSE_LOW 3
126
127/**@}*/
128
129/* GPIO Tasks and Events (GPIOTE) */
130#define GPIO_TASK_OUT(n) MMIO32(GPIOTE_BASE + 0x4 * (n))
131#define GPIO_EVENT_IN(n) MMIO32(GPIOTE_BASE + 0x100 + 0x4 * (n))
132
133#define GPIO_EVENT_PORT MMIO32(GPIOTE_BASE + 0x17C)
134
135#define GPIO_INTEN MMIO32(GPIOTE_BASE + 0x300)
136#define GPIO_INTENSET MMIO32(GPIOTE_BASE + 0x304)
137#define GPIO_INTENCLR MMIO32(GPIOTE_BASE + 0x308)
138
139#define GPIO_TE_CONFIG(n) MMIO32(GPIOTE_BASE + 0x510 + 0x4 * (n))
140
141/* Register Details */
142#define GPIO_INTEN_IN(n) (1 << (n))
143
144#define GPIO_INTEN_PORT (1 << 31)
145
146/* TODO: clean this up */
147
148#define GPIO_TE_CONFIG_MODE_SHIFT 0
149#define GPIO_TE_CONFIG_MODE_MASK 3
150
151#define GPIO_TE_CONFIG_PSEL_SHIFT 8
152#define GPIO_TE_CONFIG_PSEL_MASK 0x1f
153
154#define GPIO_TE_CONFIG_POLARITY_SHIFT 16
155#define GPIO_TE_CONFIG_POLARITY_MASK 3
156
157#define GPIO_TE_CONFIG_OUTINIT (1 << 20)
158
159#define GPIO_TE_MODE_DISABLED 0
160#define GPIO_TE_MODE_EVENT 1
161#define GPIO_TE_MODE_TASK 3
162
163#define GPIO_TE_POLARITY_NONE 0
164#define GPIO_TE_POLARITY_LO_TO_HI 1
165#define GPIO_TE_POLARITY_HI_TO_LO 2
166#define GPIO_TE_POLARITY_TOGGLE 3
167
168#define GPIO_TE_OUTINIT_LOW 0
169#define GPIO_TE_OUTINIT_HIGH 1
170
171/* GPIO number definitions (for convenience) */
172/** @defgroup gpio_pin_id GPIO Pin Identifiers
173@ingroup gpio_defines
174
175@{*/
176#define GPIO0 (1 << 0)
177#define GPIO1 (1 << 1)
178#define GPIO2 (1 << 2)
179#define GPIO3 (1 << 3)
180#define GPIO4 (1 << 4)
181#define GPIO5 (1 << 5)
182#define GPIO6 (1 << 6)
183#define GPIO7 (1 << 7)
184#define GPIO8 (1 << 8)
185#define GPIO9 (1 << 9)
186#define GPIO10 (1 << 10)
187#define GPIO11 (1 << 11)
188#define GPIO12 (1 << 12)
189#define GPIO13 (1 << 13)
190#define GPIO14 (1 << 14)
191#define GPIO15 (1 << 15)
192#define GPIO16 (1 << 16)
193#define GPIO17 (1 << 17)
194#define GPIO18 (1 << 18)
195#define GPIO19 (1 << 19)
196#define GPIO20 (1 << 20)
197#define GPIO21 (1 << 21)
198#define GPIO22 (1 << 22)
199#define GPIO23 (1 << 23)
200#define GPIO24 (1 << 24)
201#define GPIO25 (1 << 25)
202#define GPIO26 (1 << 26)
203#define GPIO27 (1 << 27)
204#define GPIO28 (1 << 28)
205#define GPIO29 (1 << 29)
206#define GPIO30 (1 << 30)
207#define GPIO31 (1 << 31)
208#define GPIO_ALL 0xffffffff
209/**@}*/
210
211/**@}*/
213
214void gpio_set(uint32_t gpioport, uint32_t gpios);
215void gpio_clear(uint32_t gpioport, uint32_t gpios);
216uint32_t gpio_get(uint32_t gpioport, uint32_t gpios);
217void gpio_toggle(uint32_t gpioport, uint32_t gpios);
218
219void gpio_mode_setup(uint32_t gpioport, uint32_t mode, uint32_t pull_up_down,
220 uint32_t gpios);
221
222void gpio_set_options(uint32_t gpioport, uint32_t drive, uint32_t sense,
223 uint32_t gpios);
224
225void gpio_configure_task(uint8_t task_num,
226 uint8_t pin_num, uint8_t polarity, uint32_t init);
227
228void gpio_configure_event(uint8_t event_num, uint8_t pin_num, uint8_t polarity);
229
230void gpio_enable_interrupts(uint32_t mask);
231void gpio_disable_interrupts(uint32_t mask);
232void gpio_clear_interrupts(void);
233
235
236
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
uint32_t gpio_get(uint32_t gpioport, uint32_t gpios)
Read GPIO values.
Definition: gpio.c:76
void gpio_configure_event(uint8_t event_num, uint8_t pin_num, uint8_t polarity)
Configure Event in GPIO TE Module.
Definition: gpio.c:175
void gpio_disable_interrupts(uint32_t mask)
Disable GPIO interrupts.
Definition: gpio.c:195
void gpio_set(uint32_t gpioport, uint32_t gpios)
Atomic set output.
Definition: gpio.c:41
void gpio_configure_task(uint8_t task_num, uint8_t pin_num, uint8_t polarity, uint32_t init)
Configure Task in GPIO TE Module.
Definition: gpio.c:155
void gpio_set_options(uint32_t gpioport, uint32_t drive, uint32_t sense, uint32_t gpios)
Configure GPIO pin input and output specifics.
Definition: gpio.c:125
void gpio_clear_interrupts(void)
Disable all GPIO interrupts.
Definition: gpio.c:203
void gpio_clear(uint32_t gpioport, uint32_t gpios)
Atomic clear output.
Definition: gpio.c:52
void gpio_toggle(uint32_t gpioport, uint32_t gpios)
Toggle output.
Definition: gpio.c:63
void gpio_enable_interrupts(uint32_t mask)
Enable GPIO interrupts.
Definition: gpio.c:186
void gpio_mode_setup(uint32_t gpioport, uint32_t mode, uint32_t pull_up_down, uint32_t gpios)
Set GPIO Pin Mode.
Definition: gpio.c:94