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#define | GPIO (GPIO_BASE) |
| GPIO port. More...
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#define | GPIO_OUT MMIO32(GPIO_BASE + 0x504) |
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#define | GPIO_OUTSET MMIO32(GPIO_BASE + 0x508) |
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#define | GPIO_OUTCLR MMIO32(GPIO_BASE + 0x50C) |
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#define | GPIO_IN MMIO32(GPIO_BASE + 0x510) |
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#define | GPIO_DIR MMIO32(GPIO_BASE + 0x514) |
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#define | GPIO_DIRSET MMIO32(GPIO_BASE + 0x518) |
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#define | GPIO_DIRCLR MMIO32(GPIO_BASE + 0x51C) |
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#define | GPIO_PIN_CNF(N) MMIO32(GPIO_BASE + 0x700 + 0x4 * (N)) |
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#define | GPIO_CNF_MODE_MASK 2 |
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#define | GPIO_CNF_MODE_SHIFT 0 |
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#define | GPIO_MODE_INPUT 0 |
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#define | GPIO_MODE_OUTPUT 1 |
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#define | GPIO_MODE_ANALOG 2 |
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#define | GPIO_CNF_PUPD_MASK 2 |
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#define | GPIO_CNF_PUPD_SHIFT 2 |
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#define | GPIO_PUPD_NONE 0x0 |
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#define | GPIO_PUPD_PULLDOWN 0x1 |
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#define | GPIO_PUPD_PULLUP 0x2 |
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#define | GPIO_CNF_DRIVE_SHIFT 8 |
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#define | GPIO_CNF_DRIVE_MASK 7 |
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#define | GPIO_CNF_DRIVE_S0S1 0 |
| Standard 0, standard 1. More...
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#define | GPIO_CNF_DRIVE_H0S1 1 |
| High drive 0, standard 1. More...
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#define | GPIO_CNF_DRIVE_S0H1 2 |
| Standard 0, high drive 1. More...
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#define | GPIO_CNF_DRIVE_H0H1 3 |
| High drive 0, high drive 1. More...
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#define | GPIO_CNF_DRIVE_D0S1 4 |
| Disconnect 0, standard 1 (wired-or connections) More...
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#define | GPIO_CNF_DRIVE_D0H1 5 |
| Disconnect 0, high drive 1 (wired-or connections) More...
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#define | GPIO_CNF_DRIVE_S0D1 6 |
| Standard 0, disconnect 1 (wired-and connections) More...
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#define | GPIO_CNF_DRIVE_H0D1 7 |
| High drive 0, disconnect 1 (wired-and connections) More...
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#define | GPIO_CNF_SENSE_SHIFT 16 |
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#define | GPIO_CNF_SENSE_MASK 3 |
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#define | GPIO_CNF_SENSE_DISABLE 0 |
| Pin sensing is disabled. More...
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#define | GPIO_CNF_SENSE_HIGH 2 |
| Pin sensing is active for high level. More...
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#define | GPIO_CNF_SENSE_LOW 3 |
| Pin sensing is active for low level. More...
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#define | GPIO_TASK_OUT(n) MMIO32(GPIOTE_BASE + 0x4 * (n)) |
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#define | GPIO_EVENT_IN(n) MMIO32(GPIOTE_BASE + 0x100 + 0x4 * (n)) |
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#define | GPIO_EVENT_PORT MMIO32(GPIOTE_BASE + 0x17C) |
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#define | GPIO_INTEN MMIO32(GPIOTE_BASE + 0x300) |
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#define | GPIO_INTENSET MMIO32(GPIOTE_BASE + 0x304) |
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#define | GPIO_INTENCLR MMIO32(GPIOTE_BASE + 0x308) |
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#define | GPIO_TE_CONFIG(n) MMIO32(GPIOTE_BASE + 0x510 + 0x4 * (n)) |
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#define | GPIO_INTEN_IN(n) (1 << (n)) |
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#define | GPIO_INTEN_PORT (1 << 31) |
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#define | GPIO_TE_CONFIG_MODE_SHIFT 0 |
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#define | GPIO_TE_CONFIG_MODE_MASK 3 |
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#define | GPIO_TE_CONFIG_PSEL_SHIFT 8 |
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#define | GPIO_TE_CONFIG_PSEL_MASK 0x1f |
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#define | GPIO_TE_CONFIG_POLARITY_SHIFT 16 |
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#define | GPIO_TE_CONFIG_POLARITY_MASK 3 |
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#define | GPIO_TE_CONFIG_OUTINIT (1 << 20) |
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#define | GPIO_TE_MODE_DISABLED 0 |
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#define | GPIO_TE_MODE_EVENT 1 |
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#define | GPIO_TE_MODE_TASK 3 |
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#define | GPIO_TE_POLARITY_NONE 0 |
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#define | GPIO_TE_POLARITY_LO_TO_HI 1 |
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#define | GPIO_TE_POLARITY_HI_TO_LO 2 |
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#define | GPIO_TE_POLARITY_TOGGLE 3 |
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#define | GPIO_TE_OUTINIT_LOW 0 |
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#define | GPIO_TE_OUTINIT_HIGH 1 |
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#define | GPIO0 (1 << 0) |
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#define | GPIO1 (1 << 1) |
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#define | GPIO2 (1 << 2) |
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#define | GPIO3 (1 << 3) |
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#define | GPIO4 (1 << 4) |
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#define | GPIO5 (1 << 5) |
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#define | GPIO6 (1 << 6) |
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#define | GPIO7 (1 << 7) |
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#define | GPIO8 (1 << 8) |
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#define | GPIO9 (1 << 9) |
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#define | GPIO10 (1 << 10) |
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#define | GPIO11 (1 << 11) |
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#define | GPIO12 (1 << 12) |
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#define | GPIO13 (1 << 13) |
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#define | GPIO14 (1 << 14) |
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#define | GPIO15 (1 << 15) |
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#define | GPIO16 (1 << 16) |
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#define | GPIO17 (1 << 17) |
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#define | GPIO18 (1 << 18) |
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#define | GPIO19 (1 << 19) |
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#define | GPIO20 (1 << 20) |
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#define | GPIO21 (1 << 21) |
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#define | GPIO22 (1 << 22) |
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#define | GPIO23 (1 << 23) |
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#define | GPIO24 (1 << 24) |
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#define | GPIO25 (1 << 25) |
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#define | GPIO26 (1 << 26) |
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#define | GPIO27 (1 << 27) |
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#define | GPIO28 (1 << 28) |
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#define | GPIO29 (1 << 29) |
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#define | GPIO30 (1 << 30) |
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#define | GPIO31 (1 << 31) |
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#define | GPIO_ALL 0xffffffff |
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