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libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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| ▼CM3 Defines | Defined Constants and Types for Cortex M3 core features |
| Debugging | Macros and functions to aid in debugging |
| ▼Cortex Core Defines | libopencm3 Defined Constants and Types for the Cortex Core |
| Cortex Core Atomic support Defines | Atomic operation support |
| Cortex-M Data Watch and Trace unit. | System Control Space (SCS) => Data Watchpoint and Trace (DWT) |
| Cortex-M Flash Patch and Breakpoint (FPB) unit | |
| Cortex-M Instrumentation Trace Macrocell (ITM) | |
| ▼Cortex-M MPU Defines | libopencm3 Cortex Memory Protection Unit |
| MPU Registers | |
| MPU TYPE register fields | The MPU_TYPE register is always available, even if the MPU is not implemented |
| MPU CTRL register fields | Defines for the Control Register |
| MPU RNR register fields | Defines for the Region Number Register |
| MPU RBAR register fields | Defines for the Region Base Address Register |
| ▼MPU RASR register fields | Defines for the Region Attribute and Size Register |
| MPU RASR Attributes | Not all attributes are available on v6m |
| ▼Cortex-M NVIC Defines | libopencm3 Cortex Nested Vectored Interrupt Controller |
| NVIC Registers | |
| Cortex M0/M3/M4 System Interrupts | IRQ numbers -3 and -6 to -9 are reserved |
| User interrupts for LPC 43xx series M0 core | |
| ▼Cortex-M System Control Block | The System Control Block is a section of the System Control Space |
| SCB Registers | |
| SCB_CPUID Values | |
| SCB_ICSR Values | |
| SCB_VTOR Values | |
| SCB_AICR Values | |
| SCB_SCR Values | |
| SCB_CCR Values | |
| ▼Cortex-M System Control Space | The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control |
| SCS Registers | |
| ▼Cortex-M SysTick Defines | libopencm3 Defined Constants and Types for the Cortex SysTick |
| ▼STK_CSR Values | |
| Clock source selection | |
| STK_RVR Values | |
| STK_CALIB Values | |
| Cortex-M Trace Port Interface Unit (TPIU) | |
| Cortex Core Peripheral APIs | APIs for Cortex Core peripherals |
| Coresight Registers | CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals |
| LPC43xx | Libraries for NXP Semiconductors LPC43xx series |
| ▼LPC43xx Defines | Defined Constants and Types for the LPC43xx series |
| ADC Defines | Defined Constants and Types for the LPC43xx A/D Converter |
| Alarm Timer Defines | Defined Constants and Types for the LPC43xx Alarm Timer |
| Clock Control Unit Defines | Defined Constants and Types for the LPC43xx Clock Control Unit |
| Clock Generation Unit Defines | Defined Constants and Types for the LPC43xx Clock Generation Unit |
| Configuration Registers Defines | Defined Constants and Types for the LPC43xx Configuration Registers |
| Event Router Defines | Defined Constants and Types for the LPC43xx Event Router |
| Global Input Multiplexer Array Defines | Defined Constants and Types for the LPC43xx Global Input Multiplexer Array |
| General Purpose DMA Defines | Defined Constants and Types for the LPC43xx General Purpose DMA |
| General Purpose I/O Defines | Defined Constants and Types for the LPC43xx General Purpose I/O |
| I2C Defines | Defined Constants and Types for the LPC43xx I2C |
| I2S Defines | Defined Constants and Types for the LPC43xx I2S |
| Reset Generation Unit Defines | Defined Constants and Types for the LPC43xx Reset Generation Unit |
| Repetitive Interrupt Timer Defines | Defined Constants and Types for the LPC43xx Repetitive Interrupt Timer |
| System Control Unit Defines | Defined Constants and Types for the LPC43xx System Control Unit |
| SDIO | Defined Constants and Types for the LPC43xx SDIO |
| Serial General Purpose I/O | Defined Constants and Types for the LPC43xx Serial General Purpose I/O |
| Synchronous Serial Port | Defined Constants and Types for the LPC43xx Synchronous Serial Port |
| Timer | Defined Constants and Types for the LPC43xx timer |
| Windowed Watchdog Timer | Defined Constants and Types for the LPC43xx Windowed Watchdog Timer |
| (M0) User interrupt service routines (ISR) prototypes for LPC 43xx series M0 core |