libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
LPC43XX
Here is a list of all modules:
[detail level 1234]
 CM3 DefinesDefined Constants and Types for Cortex M3 core features
 DebuggingMacros and functions to aid in debugging
 Cortex Core Defineslibopencm3 Defined Constants and Types for the Cortex Core
 Cortex Core Atomic support DefinesAtomic operation support
 Cortex-M Data Watch and Trace unit.System Control Space (SCS) => Data Watchpoint and Trace (DWT)
 Cortex-M Flash Patch and Breakpoint (FPB) unit
 Cortex-M Instrumentation Trace Macrocell (ITM)
 Cortex-M MPU Defineslibopencm3 Cortex Memory Protection Unit
 MPU Registers
 MPU TYPE register fieldsThe MPU_TYPE register is always available, even if the MPU is not implemented
 MPU CTRL register fieldsDefines for the Control Register
 MPU RNR register fieldsDefines for the Region Number Register
 MPU RBAR register fieldsDefines for the Region Base Address Register
 MPU RASR register fieldsDefines for the Region Attribute and Size Register
 MPU RASR AttributesNot all attributes are available on v6m
 Cortex-M NVIC Defineslibopencm3 Cortex Nested Vectored Interrupt Controller
 NVIC Registers
 Cortex M0/M3/M4 System InterruptsIRQ numbers -3 and -6 to -9 are reserved
 User interrupts for LPC 43xx series M0 core
 Cortex-M System Control BlockThe System Control Block is a section of the System Control Space
 SCB Registers
 SCB_CPUID Values
 SCB_ICSR Values
 SCB_VTOR Values
 SCB_AICR Values
 SCB_SCR Values
 SCB_CCR Values
 Cortex-M System Control SpaceThe System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control
 SCS Registers
 Cortex-M SysTick Defineslibopencm3 Defined Constants and Types for the Cortex SysTick
 STK_CSR Values
 Clock source selection
 STK_RVR Values
 STK_CALIB Values
 Cortex-M Trace Port Interface Unit (TPIU)
 Cortex Core Peripheral APIsAPIs for Cortex Core peripherals
 Coresight RegistersCoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals
 LPC43xxLibraries for NXP Semiconductors LPC43xx series
 LPC43xx DefinesDefined Constants and Types for the LPC43xx series
 ADC DefinesDefined Constants and Types for the LPC43xx A/D Converter
 Alarm Timer DefinesDefined Constants and Types for the LPC43xx Alarm Timer
 Clock Control Unit DefinesDefined Constants and Types for the LPC43xx Clock Control Unit
 Clock Generation Unit DefinesDefined Constants and Types for the LPC43xx Clock Generation Unit
 Configuration Registers DefinesDefined Constants and Types for the LPC43xx Configuration Registers
 Event Router DefinesDefined Constants and Types for the LPC43xx Event Router
 Global Input Multiplexer Array DefinesDefined Constants and Types for the LPC43xx Global Input Multiplexer Array
 General Purpose DMA DefinesDefined Constants and Types for the LPC43xx General Purpose DMA
 General Purpose I/O DefinesDefined Constants and Types for the LPC43xx General Purpose I/O
 I2C DefinesDefined Constants and Types for the LPC43xx I2C
 I2S DefinesDefined Constants and Types for the LPC43xx I2S
 Reset Generation Unit DefinesDefined Constants and Types for the LPC43xx Reset Generation Unit
 Repetitive Interrupt Timer DefinesDefined Constants and Types for the LPC43xx Repetitive Interrupt Timer
 System Control Unit DefinesDefined Constants and Types for the LPC43xx System Control Unit
 SDIODefined Constants and Types for the LPC43xx SDIO
 Serial General Purpose I/ODefined Constants and Types for the LPC43xx Serial General Purpose I/O
 Synchronous Serial PortDefined Constants and Types for the LPC43xx Synchronous Serial Port
 TimerDefined Constants and Types for the LPC43xx timer
 Windowed Watchdog TimerDefined Constants and Types for the LPC43xx Windowed Watchdog Timer
 (M0) User interrupt service routines (ISR) prototypes for LPC 43xx series M0 core