| ▼CM3 Defines | Defined Constants and Types for Cortex M3 core features |
| Debugging | Macros and functions to aid in debugging |
| ►Cortex Core Defines | libopencm3 Defined Constants and Types for the Cortex Core |
| Cortex Core Atomic support Defines | Atomic operation support |
| Cortex-M Data Watch and Trace unit. | System Control Space (SCS) => Data Watchpoint and Trace (DWT) |
| Cortex-M Flash Patch and Breakpoint (FPB) unit | |
| Cortex-M Instrumentation Trace Macrocell (ITM) | |
| ►Cortex-M MPU Defines | libopencm3 Cortex Memory Protection Unit |
| MPU Registers | |
| MPU TYPE register fields | The MPU_TYPE register is always available, even if the MPU is not implemented |
| MPU CTRL register fields | Defines for the Control Register |
| MPU RNR register fields | Defines for the Region Number Register |
| MPU RBAR register fields | Defines for the Region Base Address Register |
| ►MPU RASR register fields | Defines for the Region Attribute and Size Register |
| MPU RASR Attributes | Not all attributes are available on v6m |
| ►Cortex-M NVIC Defines | libopencm3 Cortex Nested Vectored Interrupt Controller |
| NVIC Registers | |
| Cortex M0/M3/M4 System Interrupts | IRQ numbers -3 and -6 to -9 are reserved |
| User interrupts for STM32 G0 series | |
| ►Cortex-M System Control Block | The System Control Block is a section of the System Control Space |
| SCB Registers | |
| SCB_CPUID Values | |
| SCB_ICSR Values | |
| SCB_VTOR Values | |
| SCB_AICR Values | |
| SCB_SCR Values | |
| SCB_CCR Values | |
| ►Cortex-M System Control Space | The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control |
| SCS Registers | |
| ►Cortex-M SysTick Defines | libopencm3 Defined Constants and Types for the Cortex SysTick |
| ►STK_CSR Values | |
| Clock source selection | |
| STK_RVR Values | |
| STK_CALIB Values | |
| Cortex-M Trace Port Interface Unit (TPIU) | |
| ▼Cortex Core Peripheral APIs | APIs for Cortex Core peripherals |
| DWT | libopencm3 Cortex-M Data Watchpoint and Trace unit |
| NVIC | libopencm3 Cortex Nested Vectored Interrupt Controller |
| SCB | libopencm3 Cortex-M System Control Block |
| SysTick | libopencm3 Cortex System Tick Timer |
| Coresight Registers | CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals |
| ▼Peripheral APIs | APIs for device peripherals |
| DMA peripheral API | DMA library for the multi channel controller found in F0/1/3 & L/G parts |
| FLASH peripheral API | libopencm3 STM32G0xx FLASH |
| PWR peripheral API | libopencm3 STM32G0xx Power Control |
| RCC peripheral API | libopencm3 STM32G0xx Reset and Clock Control |
| ADC peripheral API | |
| CRC peripheral API | |
| DAC peripheral API | Digital to Analog Converter |
| DMAMUX peripheral API | |
| EXTI peripheral API | |
| GPIO peripheral API | |
| I2C peripheral API | |
| IWDG peripheral API | |
| LPTIM peripheral API | |
| RNG peripheral API | This library supports "version 1" of the random number generator peripheral (RNG) in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics |
| SPI peripheral API | |
| TIMER peripheral API | |
| USART peripheral API | |
| STM32G0xx | Libraries for ST Microelectronics STM32G0xx series |
| ▼STM32G0xx Defines | Defined Constants and Types for the STM32G0xx series |
| ►ADC Defines | Defined Constants and Types for the STM32STM32G0xx Analog to Digital Converter |
| ADC register base addresses | |
| ADC Channel Numbers | |
| AWDTR1 ADC watchdog threshold register 1 | Shadows adc adc_tr1 register on other chips |
| AWDTR2 ADC watchdog threshold register 2 | |
| AWD2CR ADC Analog watchdog 2 configuration register | |
| AWD3CR ADC Analog watchdog 3 configuration register | |
| ADC clock source | |
| ADC Sampling Time | |
| ADC registers | |
| ISR ADC interrupt status register | |
| IER ADC interrupt enable register | |
| CR ADC control register | |
| ►CFGR1 ADC configuration register 1 | |
| ADC external trigger selection values | |
| EXTEN: External trigger enable and polarity selection for regular channels | |
| RES: Data resolution | |
| ►SMPR ADC sample time register | |
| ADC Sample Time selection | |
| ADC Sample Time selection values | |
| ►CFGR2 ADC configuration register 2 | |
| ADC Clock mode | |
| ADC Oversampling shift | |
| ADC Oversampling ratio | |
| TR1 ADC watchdog threshold register 1 | |
| ►CCR ADC common configuration register | |
| ADC clock prescaler | |
| CHSELR ADC Channel Selection register | |
| ►CRC Defines | Defined Constants and Types for the STM32G0xx CRC Generator |
| CRC Registers | |
| ►CRC_CR values | |
| CRC Reverse input options | |
| CRC Polynomial size | |
| ►DAC Defines | Defined Constants and Types for the STM32G0xx Digital-to-Analog Converter |
| DAC register base addresses | |
| DAC Registers | |
| ►DAC_CR values | |
| DAC Channel 2 Trigger Source Selection | |
| DAC Channel 1 Trigger Source Selection | |
| DAC_SWTRIGR Values | |
| DAC_DHRxxx Values | |
| DAC_DORx Values | |
| DAC_SR Values | |
| DAC Channel Identifier | |
| ►DMA Defines | Defined Constants and Types for the STM32G0xx DMA Controller |
| DMA Interrupt Flag Offsets within channel flag | Group |
| DMA Channel Priority Levels | |
| DMA Channel Memory Word Width | |
| DMA Channel Peripheral Word Width | |
| DMA Channel Number | |
| ►DMAMUX Defines | Defined Constants and Types for the STM32G0xx DMAMUX DMA request router |
| DMAMUX register base addresses | |
| SYNCID Synchronization input selected | |
| DMAREQID DMA request line selected | |
| SIGID DMA request trigger input selected | |
| ►CxCR DMA request line multiplexer channel x control register | |
| SPOL Event Polarity | Synchronization event type selector |
| CSR request line multiplexer interrupt channel status register | |
| CFR request line multiplexer interrupt clear flag register | |
| ►RGxCR DMA request generator channel x control register | |
| GPOL Event Polarity | DMA request generator trigger event type selection |
| RGSR DMA request generator interrupt status register | |
| RGCFR DMA request generator clear flag register | |
| DMAMUX Request Generator Channel Number | |
| ►EXTI Defines | Defined Constants and Types for the STM32G0xx EXTI Control |
| EXTI Registers | |
| ►FLASH Defines | Defined Constants and Types for the STM32G0xx Flash Control |
| FLASH Registers | |
| ►ACR Access control register | |
| FLASH Wait States | Flash memory access latency |
| KEYR Flash key register | |
| OPTKEYR Option byte key register | |
| SR Status register | |
| CR Flash control register | |
| ECCR Flash ECC register | |
| ►OPTR Flash option register | |
| NRST MODE | NRST_MODE |
| BORR LEV | These bits contain the VDD supply level threshold that releases the reset |
| BOR FLEV | These bits contain the VDD supply level threshold that activates the reset |
| RDP | Read protection level |
| ►GPIO Defines | Defined Constants and Types for the STM32G0xx General Purpose I/O |
| GPIO Output Pin Speed | |
| GPIO Pin Identifiers | |
| GPIO Port IDs | |
| GPIO Pin Direction and Analog/Digital Mode | |
| GPIO Output Pin Driver Type | |
| GPIO Output Pin Pullup | |
| Alternate Function Pin Selection | |
| ►I2C Defines | Defined Constants and Types for the STM32G0xx I2C |
| I2C register base address | |
| ►IWDG Defines | Defined Constants and Types for the STM32G0xx Independent Watchdog Timer |
| IWDG Key Values | |
| IWDG prescaler divider | |
| IWDG Status Register Values | |
| ►LPTIM Defines | libopencm3 Defined Constants and Types for the STM32G0xx Low Power Timer |
| Low Power Timer register base addresses | |
| LPTIM_CFGR2 Configuration Register 2 | |
| LPTIM_ISR Interrupt and Status Register | |
| LPTIM_ICR Interrupt Clear Register | |
| LPTIM_IER Interrupt Enable Register | |
| ►LPTIM_CFGR Configuration Register | |
| LPTIM_CFGR CKPOL Clock Polarity | |
| LPTIM_CFGR CKFLT Configurable digital filter for external clock | |
| LPTIM_CFGR TRGFLT Configurable digital filter for trigger | |
| LPTIM_CFGR PRESC Clock prescaler | |
| LPTIM_CFGR TRIGSEL Trigger selector | |
| LPTIM_CFGR TRIGEN Trigger enable and polarity | |
| LPTIM_CR Control Register | |
| ►PWR Defines | Defined Constants and Types for the STM32G0xx PWR Control |
| PWR Registers | |
| VOS | Voltage scaling range selection |
| LPMS | Low-power mode selection |
| PVDRT | Power voltage detector rising threshold selection |
| PVDFT | Power voltage detector falling threshold selection |
| ►RCC Defines | Defined Constants and Types for the STM32G0xx Reset and Clock Control |
| Reset and Clock Control Register | |
| ►CR Clock control Register | |
| HSI Div | Division factor of the HSI16 oscillator to produce HSISYS clock |
| ICSCR Internal Clock Source Calibration Register | |
| ►CFGR Configuration Register | |
| MCO Pre | Division factor of microcontroler clock output |
| MCO Sel | Microcontroler clock output selector |
| PPRE | APB Prescaler |
| HPRE | APB Prescaler |
| SWS | System clock switch status |
| SW | System clock switch |
| ►PLLCFGR PLL Configuration Register | |
| PLLR | VCO Division factor R for PLLRCLK clock output [2..8] |
| PLLQ | VCO Division factor Q for PLLQCLK clock output [2..8] |
| PLLP | VCO Division factor P for PLLPCLK clock output [2..32] |
| PLLN | Multiplication factor N [8..86] for PLL VCO output frequency |
| PLLM | Division factor M [1..8] for PLL input clock |
| PLLSRC | PLL input clock source |
| CIER Clock Interrupt Enable Register | |
| CIFR Clock Interrupt Flag Register | |
| CICR Clock Interrupt Clear Register | |
| RCC_AHBRSTR reset values | |
| ►RCC_APBRSTRx reset values (full set) | |
| RCC_APBRSTR1 reset values | |
| RCC_APBRSTR2 reset values | |
| RCC_AHBENR enable values | |
| ►RCC_APBENRx enable values (full set) | |
| RCC_APBENR1 enable values | |
| RCC_APBENR2 enable values | |
| RCC_AHBSMENR enable in sleep/stop mode values | |
| RCC_APBSMENR1 enable in sleep/stop mode values | |
| RCC_APBSMENR2 enable in sleep/stop mode values | |
| ►CCIPR Peripherals Independent Clock Config Register | |
| ADCSEL | |
| RNGDIV | |
| RNGSEL | |
| TIM15SEL | |
| TIM1SEL | |
| LPTIM2SEL LPTIM2 Clock source selection | |
| LPTIM1SEL LPTIM1 Clock source selection | |
| I2S1SEL I2S1 Clock source selection | |
| I2C1SEL I2C1 Clock source selection | |
| LPUARTxSEL LPUART1 Clock source selection | |
| CECSEL CEC Clock souce selection | |
| USARTxSEL USARTx Clock source selection | |
| ►BDCR Backup Domain Control Register | |
| RTCSEL RTC Clock source selection | |
| LSEDRV LSE Oscillator drive capacity | |
| CSR Control and Status Register | |
| RNG Defines | Defined Constants and Types for the STM32G0xx RNG Control |
| ►SPI Defines | Defined Constants and Types for the STM32G0xx SPI |
| SPI Register base address | |
| SPI lsb/msb first | |
| SPI peripheral baud rates | |
| SPI peripheral baud rate prescale values | |
| SPI clock polarity | |
| SPI clock phase | |
| SPI crc length | |
| SPI data size | |
| ►SYSCFG Defines | Defined Constants and Types for the STM32G0xx System Configuration controller |
| SYSCFG Registers |  |
| ►CFGR1 SYSCFG configuration register 1 | |
| IR MOD | IR Modulation Envelope signal selection |
| MEM MODE | Memory mapping selection bits |
| CFGR2 SYSCFG configuration register 2 | |
| ITLINE0 interrupt line 0 status register | |
| ITLINE1 interrupt line 1 status register | |
| ITLINE2 interrupt line 2 status register | |
| ITLINE3 interrupt line 3 status register | |
| ITLINE4 interrupt line 4 status register | |
| ITLINE5 interrupt line 5 status register | |
| ITLINE6 interrupt line 6 status register | |
| ITLINE7 interrupt line 7 status register | |
| ITLINE8 interrupt line 8 status register | |
| ITLINE9 interrupt line 9 status register | |
| ITLINE10 interrupt line 10 status register | |
| ITLINE11 interrupt line 11 status register | |
| ITLINE12 interrupt line 12 status register | |
| ITLINE13 interrupt line 13 status register | |
| ITLINE14 interrupt line 14 status register | |
| ITLINE15 interrupt line 15 status register | |
| ITLINE16 interrupt line 16 status register | |
| ITLINE17 interrupt line 17 status register | |
| ITLINE18 interrupt line 18 status register | |
| ITLINE19 interrupt line 19 status register | |
| ITLINE20 interrupt line 20 status register | |
| ITLINE21 interrupt line 21 status register | |
| ITLINE22 interrupt line 22 status register | |
| ITLINE23 interrupt line 23 status register | |
| ITLINE24 interrupt line 24 status register | |
| ITLINE25 interrupt line 25 status register | |
| ITLINE26 interrupt line 26 status register | |
| ITLINE27 interrupt line 27 status register | |
| ITLINE28 interrupt line 28 status register | |
| ITLINE29 interrupt line 29 status register | |
| ITLINE30 interrupt line 30 status register | |
| ITLINE31 interrupt line 31 status register | |
| ►Timer Defines | Defined Constants and Types for the STM32G0xx Timers |
| TIM_OR1_OCREF_CLR Source Selection | |
| Timer register base addresses | |
| TIMx_CR1 CKD[1:0] Clock Division Ratio | |
| TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection | |
| TIMx_CR1 DIR: Direction | |
| TIMx_CR2_OIS: Force Output Idle State Control Values | |
| TIMx_CR2 MMS[6:4]: Master Mode Selection | |
| TIMx_SMCR TS Trigger selection | |
| TIMx_SMCR SMS Slave mode selection | |
| TIMx_DIER Timer DMA and Interrupt Enable Values | |
| TIMx_SR Timer Status Register Flags | |
| TIMx_EGR Timer Event Generator Values | |
| TIM_BDTR_LOCK Timer Lock Values | |
| ►USART Defines | Defined Constants and Types for the STM32G0xx USART |
| USART register base addresses | Holds all the U(S)ART peripherals supported |
| USART Parity Selection | |
| USART Tx/Rx Mode Selection | |
| USART Stop Bit Selection | |
| USART Hardware Flow Control Selection | |
| USART Registers | |
| U(S)ART convenience Flags | We define the "common" lower flag bits using a standard name, allowing them to be used regardless of which usart peripheral version you have |
| USART_CR1 Values | |
| ►USART_CR2 Values | |
| Auto baud rate mode | ABRMOD[1:0]: Auto baud rate mode |
| USART_CR3 Values | |
| USART_GTPR Values | |
| USART_RTOR Values | |
| USART_RQR Values | |
| USART_ISR Values | |
| USART_ICR Values | |
| USART_RDR/TDR Values | |
| User interrupt service routines (ISR) prototypes for STM32 G0 series | |
| User interrupt service routines (ISR) defaults for STM32 G0 series | |
1.9.4