| ▼CM3 Defines | Defined Constants and Types for Cortex M3 core features |
| Debugging | Macros and functions to aid in debugging |
| ►Cortex Core Defines | libopencm3 Defined Constants and Types for the Cortex Core |
| Cortex Core Atomic support Defines | Atomic operation support |
| Cortex-M Data Watch and Trace unit. | System Control Space (SCS) => Data Watchpoint and Trace (DWT) |
| Cortex-M Flash Patch and Breakpoint (FPB) unit | |
| Cortex-M Instrumentation Trace Macrocell (ITM) | |
| ►Cortex-M MPU Defines | libopencm3 Cortex Memory Protection Unit |
| MPU Registers | |
| MPU TYPE register fields | The MPU_TYPE register is always available, even if the MPU is not implemented |
| MPU CTRL register fields | Defines for the Control Register |
| MPU RNR register fields | Defines for the Region Number Register |
| MPU RBAR register fields | Defines for the Region Base Address Register |
| ►MPU RASR register fields | Defines for the Region Attribute and Size Register |
| MPU RASR Attributes | Not all attributes are available on v6m |
| ►Cortex-M NVIC Defines | libopencm3 Cortex Nested Vectored Interrupt Controller |
| NVIC Registers | |
| Cortex M0/M3/M4 System Interrupts | IRQ numbers -3 and -6 to -9 are reserved |
| User interrupts for PAC55XX Series | |
| ►Cortex-M System Control Block | The System Control Block is a section of the System Control Space |
| SCB Registers | |
| SCB_CPUID Values | |
| SCB_ICSR Values | |
| SCB_VTOR Values | |
| SCB_AICR Values | |
| SCB_SCR Values | |
| SCB_CCR Values | |
| ►Cortex-M System Control Space | The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control |
| SCS Registers | |
| ►Cortex-M SysTick Defines | libopencm3 Defined Constants and Types for the Cortex SysTick |
| ►STK_CSR Values | |
| Clock source selection | |
| STK_RVR Values | |
| STK_CALIB Values | |
| Cortex-M Trace Port Interface Unit (TPIU) | |
| ▼Cortex Core Peripheral APIs | APIs for Cortex Core peripherals |
| DWT | libopencm3 Cortex-M Data Watchpoint and Trace unit |
| NVIC | libopencm3 Cortex Nested Vectored Interrupt Controller |
| SCB | libopencm3 Cortex-M System Control Block |
| SysTick | libopencm3 Cortex System Tick Timer |
| Coresight Registers | CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals |
| ▼Peripheral APIs | APIs for device peripherals |
| Clock Control System API | PAC5xx CCS Driver |
| GPIO Peripheral API | GPIO Application Programming Interface |
| Memory Controller API | PAC5xx MEMCTL Driver |
| USART peripheral API | PAC55xxxx USART Driver |
| CAN Peripheral API | CAN Application Programming Interface |
| ▼PAC55xx Defines | Defined Constants and Types for the PAC55xx series |
| ►Clock Config and System Defines | Clock Control and System Defines for the Qorvo PAC55xx series of microcontrollers |
| CCS Frequencies | |
| Clock Control Register | |
| CCS PLL Control Register | |
| Ring Oscillator Trim Control Register | |
| Port Pinmux Register Base. | Port Pin Config Addresses |
| PMUXSEL register mapping. | Port Pin Mux Select Registers |
| PUEN PDEN register mapping. | Port Pull-Up/Down Enable Registers |
| DSR register mapping. | Port Drive Strength Enable Registers |
| ►Peripheral Memory Map | |
| Address Memory Map. | |
| Core Peripheral Memory Map. | |
| System Peripheral Memory Map. | |
| ►CAN | CAN definitions for the Qorvo PAC55xx series of microcontrollers |
| CAN ISR/SR/CMR/MR Registers | |
| CAN BTR1/BTR0/RMC/IMR Registers | |
| CAN ALC/TXERR/RXERR/ECC Registers | |
| CAN Mode Register | CAN Mode Register bit definitions |
| CAN Command Register | CAN Command Register |
| CAN Status Register | CAN Status Register |
| CAN Interrupt Status Register | CAN Interrupt Status Register bit definitions |
| CAN Mask Register | CAN Interrupt Mask Register bit definitions |
| CAN Receive Message Counter Register. | CAN Receive Message Counter Register bit definitions |
| CAN Bus Timing 0 Register. | CAN Bus Timing 0 Register bit definitions |
| CAN Bus Timing 1 Register | CAN Bus Timing 1 Register bit definitions |
| CAN Error Code Capture Register | CAN Error Code Capture Register bit definitions |
| CAN Acceptance Code Register | CAN Acceptance Code/Mask Register |
| CAN Miscellaneous Bit Masks | |
| ►GPIO | GPIO definitions for the Qorvo PAC55xx series of microcontrollers |
| GPIO Port IDs | GPIO port base addresses (for convenience) |
| GPIO Pin Identifiers | GPIO number definitions (for convenience) |
| GPIO MODE register mapping. | GPIO Mode Register Definitions |
| GPIO OUTMASK register mapping. | GPIO Output Mask Register Definitions |
| GPIO OUT register mapping. | GPIO Output Register Definitions |
| GPIO IN register mapping. | GPIO Input Register Definitions |
| GPIO INTEN register mapping. | GPIO Interrupt Enable Register Definitions |
| GPIO INTFLAG register mapping. | GPIO Interrupt Flag Register Definitions |
| GPIO INTCLEAR register mapping. | GPIO Interrupt Clear Register Definitions |
| GPIO INTTYPE register mapping. | GPIO Interrupt Type Register Definitions |
| GPIO INTCFG register mapping. | GPIO Interrupt Config Register Definitions |
| GPIO INTEDGEBOTH register mapping. | GPIO Interrupt Edge Both Definitions |
| GPIO CLKSYNC register mapping. | GPIO Clock Synchronization Settings |
| GPIO DOSET register mapping. | GPIO Set Register |
| GPIO DOCLEAR register mapping. | GPIO Set Register |
| ►Memory Controller Defines | Memory Controller definitions for the Qorvo PAC55xx series of microcontrollers |
| Memory Controller Configuration Register | |
| Memory Controller Status Register | |
| Flash Lock/Write Enable Register values | |
| Flash Erase Enable Register values | |
| ►USART | USART definitions for the Qorvo PAC55xx series of microcontrollers |
| Registers | |
| Interrupt Enable Register bits | |
| Interrupt ID Register bits | |
| FIFO Control Register bits | |
| Line Control Register bits | |
| Line Status Register bits | |
| User interrupt service routines (ISR) prototypes for PAC55XX Series | |
| User interrupt service routines (ISR) defaults for PAC55XX Series | |
1.9.4