CAN BTR1/BTR0/RMC/IMR Registers
Collaboration diagram for CAN BTR1/BTR0/RMC/IMR Registers:
Macros | |
| #define | CAN_BTR1_BTR0_RMC_IMR(can_base) MMIO32((can_base) + 0x0004) |
| This is the 32-bit memory mapped read/write accessor for: More... | |
Detailed Description
Macro Definition Documentation
◆ CAN_BTR1_BTR0_RMC_IMR
| #define CAN_BTR1_BTR0_RMC_IMR | ( | can_base | ) | MMIO32((can_base) + 0x0004) |
This is the 32-bit memory mapped read/write accessor for:
- BTR1 - bits 31:24 - Bus Timing 1 Register RW, default 00h
- BTR0 - bits 23:16 - Bus Timing 0 Register RW, default 00h
- RMC - bits 15:8 - Receive Message Counter RO, default 00h
- IMR - bits 7:0 - Interrupt Mask Register RW, default 00h
