Collaboration diagram for Registers:

Macros
#define	USART_RBR(usart_base) MMIO32((usart_base) + 0x0000)
	Receive Buffer Register RO, only bits 7:0 used. More...

#define	USART_THR(usart_base) MMIO32((usart_base) + 0x0004)
	Transmit Holding Register WO, only bits 7:0 used. More...

#define	USART_DLR(usart_base) MMIO32((usart_base) + 0x0008)
	Divisor Latch Register RW, default 0000 0001h, only bits 15:0 used. More...

#define	USART_IER(usart_base) MMIO32((usart_base) + 0x000C)
	Interrupt Enable Register RW, default 0000 0000h. More...

#define	USART_IIR(usart_base) MMIO32((usart_base) + 0x0010)
	Interrupt Identification Register RO, default 0000 0001h. More...

#define	USART_FCR(usart_base) MMIO32((usart_base) + 0x0014)
	FIFO Control Register RW, default 0000 0000h. More...

#define	USART_LCR(usart_base) MMIO32((usart_base) + 0x0018)
	Line control Register RW, default 0000 0000h. More...

#define	USART_LSR(usart_base) MMIO32((usart_base) + 0x0020)
	Line Status Register RO, default 0000 0060h. More...

#define	USART_SCR(usart_base) MMIO32((usart_base) + 0x0028)
	Scratch Pad Register RW, only bits 7:0 used. More...

#define	USART_EFR(usart_base) MMIO32((usart_base) + 0x002C)
	Enhanced Mode Register RW, default 0000 000h. More...

Detailed Description

Macro Definition Documentation

◆ USART_DLR

#define USART_DLR ( usart_base ) MMIO32((usart_base) + 0x0008)

Divisor Latch Register RW, default 0000 0001h, only bits 15:0 used.

Definition at line 47 of file usart.h.

◆ USART_EFR

#define USART_EFR ( usart_base ) MMIO32((usart_base) + 0x002C)

Enhanced Mode Register RW, default 0000 000h.

Definition at line 61 of file usart.h.

◆ USART_FCR

#define USART_FCR ( usart_base ) MMIO32((usart_base) + 0x0014)

FIFO Control Register RW, default 0000 0000h.

Definition at line 53 of file usart.h.

◆ USART_IER

#define USART_IER ( usart_base ) MMIO32((usart_base) + 0x000C)

Interrupt Enable Register RW, default 0000 0000h.

Definition at line 49 of file usart.h.

◆ USART_IIR

#define USART_IIR ( usart_base ) MMIO32((usart_base) + 0x0010)

Interrupt Identification Register RO, default 0000 0001h.

Definition at line 51 of file usart.h.

◆ USART_LCR

#define USART_LCR ( usart_base ) MMIO32((usart_base) + 0x0018)

Line control Register RW, default 0000 0000h.

Definition at line 55 of file usart.h.

◆ USART_LSR

#define USART_LSR ( usart_base ) MMIO32((usart_base) + 0x0020)

Line Status Register RO, default 0000 0060h.

Definition at line 57 of file usart.h.

◆ USART_RBR

#define USART_RBR ( usart_base ) MMIO32((usart_base) + 0x0000)

Receive Buffer Register RO, only bits 7:0 used.

Definition at line 43 of file usart.h.

◆ USART_SCR

#define USART_SCR ( usart_base ) MMIO32((usart_base) + 0x0028)

Scratch Pad Register RW, only bits 7:0 used.

Definition at line 59 of file usart.h.

◆ USART_THR

#define USART_THR ( usart_base ) MMIO32((usart_base) + 0x0004)

Transmit Holding Register WO, only bits 7:0 used.

Definition at line 45 of file usart.h.

Macros